Introduction

A Device Tree is a data structure that describes the underlying hardware to an operating system – primarily Linux.By passing this data structure the OS kernel, a single OS binary may be able to support many variations of hardware. This flexibility is particularly important when the hardware includes an FPGA.

The Device Tree Generator tool is part of Altera SoC EDS and is used to create device trees for SoC systems that contain FPGA designs created using Qsys. The generated Device Tree describes the HPS peripherals, selected FPGA Soft IP and also peripherals that are board dependent.The Altera SoC EDS can be downloaded from https://www.altera.com/download/software/soc-eds.

User Guides

• Device Tree Generator v13.1 - User Guide
• Device Tree Generator v14.0 - User Guide
• Device Tree Generator v14.1 - User Guide
• Device Tree Generator v15.0 - User Guide
• Device Tree Generator v15.1 (and newer) - User Guide

Warning

The Linux Device Tree Generator is tested with and supports only the Linux kernel version targeted by the associated GSRD. For the current 16.1 GSRD release this 4.1.22-ltsi. It is not recommended to use the Linux Device Tree Generator if your design targets a different Linux kernel version. It is instead recommended to manage the Device Tree manually in such a case, using the Device Tree files provided by the kernel as a baseline, and adding the FPGA IP and board information manually.