Compiling Hardware Design

How to compile the FPGA Hardware design that is delivered as part of the GSRD release

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Overview

The compilation will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svd	System View Description File - describes the hardware for the DS-5 debugger
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

Prerequisites

The following items are required:

• Host PC running Linux (CentOS 6.5 or Ubuntu 12.04LTS)
• Altera Quartus™ II v14.1 b186 - http://www.altera.com/products/software/sfw-index.jsp
• GHRD v14.1 Archive from https://releases.rocketboards.org/2014.12/gsrd/hw

Procedure

The procedure described below uses the Cyclone V GHRD. The procedure for Arria V GHRD is similar, with only the file names being changed:

File	Cyclone V	Arria V
GHRD Archive	cv_soc_devkit_ghrd.tar.gz	av_soc_devkit_ghrd.tar.gz
Quartus Project	~/cv_soc_devkit_ghrd/soc_system.qpf	~/av_soc_devkit_ghrd/ghrd_5astfd5k3.qpf
Qsys File	~/cv_soc_devkit_ghrd/soc_system.qsys	~/av_soc_devkit_ghrd/ghrd_5astfd5k3.qsys
Programming File	~/cv_soc_devkit_ghrd/output_files/soc_system.sof	~/av_soc_devkit_ghrd/output_files/ghrd_5astfd5k3.sof

Open Quartus Project

1. Retrieve and the archive file cv_soc_devkit_ghrd.tar.gz containing the hardware design and save it in the home folder. The file is available at https://releases.rocketboards.org/2014.12/gsrd/hw.

2. Extract the files from the archive

$ cd ~
$ tar xzf cv_soc_devkit_ghrd.tar.gz

3. Make all the files writable (optional)

$ chmod +w -R ~/cv_soc_devkit_ghrd/

4. Start Quartus tool by double clicking the icon on the desktop, or by running it from the command line:

$ ~/altera/14.1/quartus/bin/quartus --64bit 

5. In Quartus, go to File → Open Project ..., browse to the file ~/cv_soc_devkit_ghrd/soc_system.qpf and click Open.

6. Quartus will load the project.

Generate System in Qsys

7. In Quartus, go to Tools → Qsys to start the Qsys tool

8. Qsys tool will start and ask you to open a Qsys file. Select ~/cv_soc_devkit_ghrd/soc_system.qsys and click Open.

9. Qsys will load the file

10. In Qsys, select Generate → Generate HDL.. this will open the Generate dialogue box.

11. In the Generate dialogue box, click the Generate button.

12. A message will be displayed when the generation is complete (may take a few minutes depending on host machine speed)

13. Click Close button in the Generation window to close it.

14. In Qsys, go to File → Exit to close Qsys.

Compile the Design in Quartus

Running Analysis & Synthesis

15. In Quartus, in the Tasks panel change the flow from RTL Simulation to Compilation.

Running the Assembler

17. In the Tasks panel, select Assembler, right click it and select Start.

18. After the assembly phase is completed, a notification message will be displayed.

Generated Files

This section presents the name and location of the files resulted from compiling the hardware design.

File	Description
~/cv_soc_devkit_ghrd/output_files/soc_system.sof	SRAM Object File - for programming FPGA
~/cv_soc_devkit_ghrd/soc_system.sopcinfo	SOPC Info File - Used by Device Tree Generator
~/cv_soc_devkit_ghrd/soc_system/synthesis/soc_system_hps_0_hps.svd	System View File - Used by ARM DS-5 AE
~/cv_soc_devkit_ghrd/hps_isw_handoff	Handoff folder - Used by Preloader Generator

#ConvertRbf

Converting .sof to .rbf

The SOF (SRAM Object File) file can use used to program the FPGA from the Quartus Programmer tool.

However, for the purpose of programming the FPGA from software, the SOF file needs to be converted to a RBF (Raw Binary File) format.

Several different options are available for converting the file:

A. Using the command line tools from Quartus Programmer (installed by default with the SoCEDS and ARM Development Studio or installed standalone) or from Quartus.

 $ ~/altera/14.1/quartus/bin/quartus_cpf -c \
  ~/cv_soc_devkit_ghrd/output_files/soc_system.sof  \
  ~/cv_soc_devkit_ghrd/output_files/soc_system.rbf 

 $ ~/altera/14.1/qprogrammer/bin/quartus_cpf -c \
  ~/cv_soc_devkit_ghrd/output_files/soc_system.sof  \
  ~/cv_soc_devkit_ghrd/output_files/soc_system.rbf 

B. Using the GUI converter, callable from either Quartus Programmer or Quartus by selecting the menu File → Convert Programming Files.

1. Select the Programming File Type to be Raw Binary File (.rbf)
2. Select the Mode to be Fast Passive Parallel X8 or 16
3. Click on the SOF Data then click Add File and browse to the soc_system.sof file
4. Edit the desired name of the output file to be soc_system.rbf
5. Click the Generate button