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Generating and Compiling the Preloader How to generate and compile the Preloader, based on the handoff information from Quartus.
Configuration
Board(s):
Altera Cyclone V SoC BoardAltera Arria V SoC BoardTools Version(s):
17.0std, 17.1std, 18.0std, 18.1std, 17.0std, 17.1std, 18.0std, 18.1std- Select a different Task
Recent Changes
-
Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices -
Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series ~
-
Remote FPGA Debug for Stratix 10
Remote FPGA Debug over Ethernet for Stratix 10 -
Remote FPGA Debug for Agilex 7
Remote FPGA Debug over Ethernet for Agilex 7
-
GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile)
Golden System Reference Design for DK SI AGF014EA
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Overview
Note: It is highly recommended preloader and u-boot are built from the same commit.
Prerequisites
The following are required in order to be able to fully exercise the Golden System Reference Design (GSRD) User Manuals:- Host PC running Linux (CentOS 6.8 or Ubuntu 14.04LTS)
- Intel SoC EDS std - from http://www.altera.com/products/software/sfw-index.jsp
- GHRD Release - from https://releases.rocketboards.org/
Reference Information
For detailed information about the Preloader Generator see SoC EDS User GuideProcedure
The procedure shown below uses the Cyclone V GHRD as an example. The procedure for Arria V GHRD is identical, with only file names being changed.Generating the Preloader
1. Compile the GHRD as described in Compiling the Hardware Design to obtain the handoff folder. 2. Start an Embedded Command Shell and go to GHRD folder (assumed here to be saved in the home folder):$ ~/intelFPGA/3. Start the Preloader Generator aka BSP Editor/embedded/embedded_command_shell.sh $ cd ~/cv_soc_devkit_ghrd
$ bsp-editor &4. In the BSP Editor, select File → New BSP ...
5. In the New BSP window, click the ... browse button to browse to the handoff folder
6. Select the cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 folder and Click Open.
7. The New BSP window will have all the settings populated, based on the handoff folder. Accept the default settings and click OK. This will close the window.
8. In the BSP Editor window, edit any settings if necessary, then click Generate.
9. The message panel on the bottom will indicate the status of the generation. Click Exit to close the BSP Editor.
The following items are generated in the cv_soc_devkit_ghrd/software/spl_bsp/ folder | File | Description |
|---|---|
| generated | Folder containing source code that was generated based on the information from the handoff folder |
| settings.bsp | Preloader settings file, that contains the settings from the Preloader Generator |
| Makefile | Makefile used to build the Preloader |
| preloader.ds | ARM DS-5 AE that can be used to load the Preloader |
Compiling the Preloader
1. Start an Embedded Command Shell and go to the generated Preloader folder:$ ~/intelFPGA/2. Run make command to build the Preloader image/embedded/embedded_command_shell.sh $ cd ~/cv_soc_devkit_ghrd/software/spl_bsp
$ makeThe Makefile (also created by the Preloader Generator) performs the following steps:
- Extract the fixed part of the Preloader source code
- Build the Preloader executable using the fixed and the generated parts of the Preloader source code
- Convert the executable to binary, then add the bootROM required header on top of it
| File | Description |
|---|---|
| uboot-socfpga/spl/u-boot-spl | Preloader ELF file |
| uboot-socfpga/spl/u-boot-spl.bin | Preloader binary file |
| preloader-mkpimage.bin | Preloader image with the BootROM required header |
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