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Compiling Hardware Design How to re-compile the hardware design
Configuration
Board(s):
Altera Arria 10 SoC BoardTools Version(s):
15.0.1- Select a different Task
Recent Changes
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Arria 10 SoC GSRD
Arria 10 SoC Golden System Reference Design - Intel FPGA HPS Embedded Software Release Notes
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Building Bootloader for Stratix10
Building latest bootloaders for Stratix 10 SoC Devices -
Building Bootloader for Agilex 7
Building latest bootloaders for Agilex 7 SoC Devices -
Stratix10 Configuring FPGA Fabric From Linux
Configuring FPGA fabric from Linux with device tree overlays
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Overview
This page presents how to re-compile the hardware design that comes with <nop>SoC EDS 15.0. This may be needed in case any changes are made to the design. Otherwise the pre-compiled design can be used as-is.Prerequisites
The following items are required:- Host PC running Linux (CentOS 6.5 or Ubuntu 12.04LTS)
- Altera Quartus™ II v15.0 - http://www.altera.com/products/software/sfw-index.jsp
- GHRD v15.0.1 Archive from https://releases.rocketboards.org/2015.06/gsrd/hw
Compiling Hardware Design
1. Retrieve and the archive file a10_soc_devkit_ghrd.tar.gz containing the hardware design and save it in the home folder. The file is available at https://releases.rocketboards.org/2015.06/gsrd/hw. 2. Extract the files from the archive$ cd ~ $ tar xzf a10_soc_devkit_ghrd.tar.gz3. Start Quartus II
$ ~/altera/15.0/quartus/bin/quartus --64bit
4. In Quartus open the hardware project by going to File → Open Project ... Then browse to ~a10_soc_devkit_ghrd/ghrd_10as066n2.qpf and click Open.
5. In Quartus, start Qsys by going to Tools → Qsys.
6. The tool will ask to select a file to open. Select the file ~/a10_soc_devkit_ghrd/ghrd_10as066n2.qsys and click Open.
7. QSys will load the file, displaying a progress bar. Once file is loaded, Qsys will display the system.
8. In Qsys, click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.
9. Qsys will generate the system, displaying a progress bar.
10. Once complete, Qsys will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Qsys window.
11. Click Finish to close the Qsys window and get back to main Quartus window.
12. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project
13. When compilation is completed, Quartus will display the status.
The following will be created: - ~/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof - FPGA configuration file
- ~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree
Convert Programming File
The sof file produced by compiling the hardware design needs to be converted to the rbf format required by the U-Boot. It is also split into two different files:- peripheral file - for configuring the IO ring
- core file - for configuring the FPGA fabric
$ ~/altera/15.0/embedded/embedded_command_shell.sh2. Go to the GHRD folder
$ cd ~/a10_soc_devkit_ghrd/3. Convert the file
$ quartus_cpf -c --hps -o bitstream_compression=on output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbfThis will create the following files in the ~/a10_soc_devkit_ghrd/output_files/ folder:
- ghrd_10as066n2.periph.rbf - IO ring configuration file
- ghrd_10as066n2.core.rbf - FPGA fabric configuration file
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