This page provides an example on how to boot from FPGA on the Altera Cyclone V Development Kit.

Introduction

The HPS boot flow typically consists of the following stages:

1. BootROM
2. Preloader
3. Bootloader
4. Operating System

The Preloader is typically loaded from Flash memory by the BootROM.

When booting from FPGA, the Preloader is executed directly from FPGA memory instead of being loaded from the flash memory then executed.

For more details about the boot process please refer to:

• Boot Flow
• Cyclone V Booting and Configuration
• Arria V Booting and Configuration

Overview

The HPS (Hard Processor System) can boot from Flash memory or directly from FPGA memory.

In order to achieve booting from FPGA the following are required:

• BSEL needs to be set to 0x1 - Boot from FPGA
• FPGA image needs to have an on-chip memory instantiated, mapped at offset 0x0 behind the HPS2FPGA bridge. The memory needs to be loaded with Preloader executable binary.
• FPGA image needs to drive the value of the following two signals to HPS, since they are required by BootROM:
  • f2h_boot_from_fpga_ready - indicates that the BootROM can boot from FPGA if BSEL = 0x1
  • f2h_boot_from_fpga_on_failure - indicates that the BootROM can boot from FPGA as a fallback, if it failed booting from the selected BSEL.
• Preloader executable .text section needs to be linked to address 0xC000_0000 (equivalent of offset 0x0 behind the HPS2FPGA bridge)
• Preloader executable .data sections need to be linked to address 0xFFFF_0000 (the HPS OCRAM)

The complete flow is described in the following diagram:

Note that the design needs to be compiled once in order to obtain the handoff folder, which is used to generate the Preloader. Once the Preloader hex file is obtained, the design is compiled again in order to have the FPGA memory initialized with the contents of the hex file.

Hardware Design

This section presents a very simple design that allows booting from FPGA.For convenience, the design files are attached at the bottom of this page.

The design is based on Altera GHRD, but has a reduced number of components:

• HPS - Hard Processor Instance
• SysID - System ID
• HPS Boot Memory - FPGA memory used to store Preloader binary
• Clk - Clock and Reset source

The HPS Component needs to be configured to enable the Boot from FPGA signals as shown in the screenshot below:

The HPS Boot Memory needs to be set to 8bit witdh, and be initialized with a hex file containing the Preloader image.The following screenshot shows the memory settings that were used for this example. Note the Preloader image is stored in the file named software/spl_bsp/preloader.hex.

The following picture presents the Qsys system, showing how components are integrated in the design. Note the following:

• The HPS's f2h_boot_from_fpga bus was exported by double-clicking the corresponding cell in the Export column.
• The HPS Boot Memory was connected to the h2f AXI bus
• The HPS Boot Memory was set to a base address of 0x000_0000

The f2h_boot_from_fpga signals need to be tied at the top level to the proper values. For this example they were tied like this in the file rd_top.v:

// SoC sub-system module
soc_system soc_inst (

  …
  .hps_0_f2h_boot_from_fpga_boot_from_fpga_ready        (1'b1),
  .hps_0_f2h_boot_from_fpga_boot_from_fpga_on_failure   (1'b0)
); 

See Compiling Hardware Design for complete instructions on how to compile the hardware design.

Preloader

The Preloader needs to be instructed that it will reside in the FPGA memory. In order to achieve this, the option EXE_ON_FPGA needs to be checked in the Preloader Generator GUI before clicking the Generate button, as shown in the following screenshot:

The following two files use the above option to affect how the Preloader is linked:

1. File uboot-socfpga/board/altera/socfpga_cyclone5/build.h defines the CONFIG_PRELOADER_EXE_ON_FPGA macro and sets the base address of the data section to be in the HPS OCRAM:

#define CONFIG_PRELOADER_EXE_ON_FPGA      (1)
#define CONFIG_FPGA_DATA_BASE 0xFFFF0000

2. File uboot-socfpga/include/configs/socfpga_cyclone5.h defines the base address of the text section accordingly:

#if (CONFIG_PRELOADER_EXE_ON_FPGA == 1)
#define CONFIG_SPL_TEXT_BASE      0xC0000000
#else
#define CONFIG_SPL_TEXT_BASE      0xFFFF0000
#endif

For complete instructions on how to generate the Preloader, please refer to Generating and Compiling the Preloader.

After compiling the Preloader, the ELF image needs to be converted to hex format, to be used by Quartus tools to synthesize the FPGA memory. The hex file will need to be zero-based as the FPGA memory is located at offset zero on the HPS2FPGA bridge, while the Preloader ELF is linked to address 0xC000_0000 as seen from the HPS point of view. The command to achieve the conversion is:

$ ~/altera/13.1/embedded/embedded_command_shell.sh
$ cd ~/cv_soc_devkit_ghrd/software/spl_bsp
$ arm-none-eabi-objcopy -O ihex --adjust-vma -0xc0000000 uboot-socfpga/spl/u-boot-spl preloader.hex

Running the Demo

1. Retrieve and unpack the hardware design:

$ wget http://www.rocketboards.org/pub/Documentation/BootFromFPGA131/cv_soc_devkit_boot_fpga_rd.tar.gz
$ tar xvzf cv_soc_devkit_boot_fpga_rd.tar.gz

The hardware design has all necessary files to recompile the hardware design and re-generate the Preloader, but for the demo we will just use the included sof file: cv_soc_devkit_boot_fpga_rd/output_files/soc_system.sof.

2. Retrieve and unpack the SD card image and write it to the micro SD card:

$ wget http://www.rocketboards.org/pub/Documentation/BootFromFPGA131/boot_fpga_sd_card.img.gz
$ gunzip boot_fpga_sd_card.img.gz
$ sudo dd if=boot_fpga_sd_card.img of=/dev/sdx bs=1M
$ sudo sync

Replace /dev/sdx with the name of the SD card on your host system.

3. Configure the Cyclone V board to boot from FPGA:

Jumper	Setting
J28	left shorted
J29	right shorted
J30	right shorted

See the rest of the board configuration at Booting Linux from SD Card.

4. Insert the micro SD card in the slot.

5. Power up the board. BootROM will not find a suitable image on the FPGA since the FPGA is not yet configured. Therefore the HPS will keep being reset by the watchdog and try again and again until there is a proper image on the FPGA.

6. Program the FPGA with the cv_soc_devkit_boot_fpga_rd/output_files/soc_system.sof file by using the Quartus Programmer. See complete instructions at Programming FPGA With Quartus Programmer.

7. Once FPGA is programmed, the BootROM will recognize the boot_from_fpga signals, and will run the Preloader from FPGA memory. Then the Preloader will load the U-Boot from SD card which in turn will load and run Linux from the SD Card.

The messages on the serial console will look similar to the following:

U-Boot SPL 2013.01.01 (Nov 14 2013 - 13:43:04)
BOARD : Altera SOCFPGA Cyclone V Board
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
ALTERA DWMMC: 0

U-Boot 2013.01.01-00041-g1740999 (Nov 15 2013 - 09:47:22)
CPU   : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
DRAM:  1 GiB
MMC:   ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   mii0
Warning: failed to set MAC address

Hit any key to stop autoboot:  0
reading u-boot.scr
** Unable to read file u-boot.scr **
Optional boot script not found. Continuing to boot normally
reading zImage
3274744 bytes read in 1108 ms (2.8 MiB/s)
reading socfpga.dtb
16759 bytes read in 11 ms (1.5 MiB/s)
## Flattened Device Tree blob at 00000100
   Booting using the fdt blob at 0x00000100
   Loading Device Tree to 03ff8000, end 03fff176 … OK

Starting kernel …

Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
…
Stopping Bootlog daemon: bootlogd.

Poky 8.0 (Yocto Project 1.3 Reference Distro) 1.3 socfpga ttyS0

socfpga login: root
root@socfpga:~# 

Files

File Name	Description
cv_soc_devkit_boot_fpga_rd.tar.gz	Hardware design sources and sof file, Preloader settings and Preloader hex file
boot_fpga_sd_card.img.gz	SD Card image with U-Boot, Linux kernel and Root filesystem (no Preloader)