Lark Evaluation Board

Product Overview

Lark Board is an EVB (Evaluation Board) designed by Embest based on an Altera ARM (Cortex-A9 dual-core)+FPGA processor for areas such as medical instruments, video surveillance and industrial control. It has 1GB DDR3 SDRAM (for ARM) and 1GB DDR3 SDRAM (for FPGA), provides 4 high-speed USB2.0 Host interfaces, a TF card slot for mass storage, a 12-bit camera interface, a VGA interface, a 24-bit LCD interface, PCIe, UART, JTAG, 3G SDI input/output and a HDMI interface. Additionally, two 2 x 40-pin connectors are mounted on the board in order to make the unused pins of HPS/FPGA available for users.

System Block Diagram

General Features

Lark Board uses a SoC chip from Altera Cyclone V SX family. It has three core recourses: general-purpose IO and logic of traditional FPGA, general-purpose IO and controller of traditional ARM, and high-speed differential transceiver. The peripheral interfaces on Lark Board are designed accordingly for these resources. The main expansion and custom applications include:

• On-board USB Blaster II and JTAG in-circuit debugging
• TF card and eMMC Booting
• HPS and FPGA each has its own 1GB DDR3 memory
• SDI high-definition input/output
• VGA and HDMI high-definition display
• Medium and small-sized LCD touch screen (4.3" and 7’’)
• High-bandwidth analog front-end and ADC sampling
• 10/100/1000Mbps Ethernet
• USBX4
• Digital camera
• PCIe X1/X4
• RTC clock
• HPS expansion interfaces (QSPI, UART, SPI, I2C and GPIO)
• FPGA high-speed transceiver extended (LVDS, RSDS, SLVS, mini-LVDS)
• Linux kernel v3.10, u-boot v2013.01.01

Peripheral Interfaces

On Board USB Blaster II

JTAG and USB Blaster II are the basic debugging approaches in FPGA development. As a strategic partner of Altera, Embest has been authorized to integrate USB Blaster II on Lark Board so as to increase the efficiency and reliability of FPGA debugging, save users the trouble of purchasing an external Blaster, and therefore prevent damage to the board caused by hot plugging of external Blasters. The on-board USB Blaster supports Quartus II and ARM DS-5 development environments.

TF Card &Emmc Booting

Lark Board has a TF card slot and a 4GB eMMC, both can be used to boot the system.

DDR3 Memory

The SoC on Lark Board integrates an individual hard DDR3 controller respectively for FPGA and HPS, each of which is connected to a DDR3 memory chip (1GB). FPGA and HPS are internally bridged to realize mutual access to 1GB memory space at most at a speed of up to 400MHz (800Mbps).

SDI Transceiver

By utilizing the transceiver of SoC, LMH0303 cable driver and LMH0384 equalizer on the board, a SMB coaxial cable can be used on Lark Board to connect high-definition IP camera or DVR in the applications such as security monitoring, medical imaging and automobile safety.

VGA & HDMI

Lark Board has a CH7033B HDTV/VGA/DVI encoder, flexible image scaling engine and simple interfaces for digital audio configuration. As for video, it supports 1080 HDMI output and VGA display of up to 1920x1080 resolution. For audio, it features SPDIF and dual-channel I2S audio input and Hi-Fi audio decoding engine with up to 192k/2ch sampling rate, and supports PCB coded data and Dolby/DTC digital audio.

LNA and ADC Sampling

Lark Board integrates a dual-channel 3.3GHz RF/IF differential amplifier and a 12-bit 105MSPS ADC to implement amplification, filtering and sampling of RF/IF analog signal. By taking advantage of these resources and the powerful calculation and image processing capability of HPS&FPGA, users may develop data acquisition, analysis and processing systems such as sampling oscilloscopes, SDR (Software Defined Radio) base station, analog/digital TV reception, and GPS/radar/sonar reception and process systems.

10/100/1000 Mbps Ethernet

Lark Board has a AR8035 – a single-port10/100/1000Mbps Ethernet controller which supports RGMII interface at MAC end, delivering a low-cost and low-power network solution.

USB PHY & Hub x 4

Lark Board includes a high-speed USB 2.0 physical-layer transceiver USB3320 and an USB hub USB2514. It supports up to 4 USB interfaces and can easily implement Host/Slave/OTG functionality included in USB protocol, as well as high-speed, full-speed and low-speed transmission modes.

Digital Camera

Lark Board has a 30-pin digital camera interface which can be extended through FPC and supports 12-bit digital image input.

PCIe X1/X4 Extend

Lark Board provides a PCI-E X1/X4 expansion slot. By configuring the FPGA’s hardcore, PCI-E add-on cards can be connected to the board through the slot.

RTC Clock

There is a DS3231 clock chip on Lark Board. It is powered by a 3V coin battery to maintain system clock when system power is not available.

HPS Extend (QSPI, SPI, I2C, UART, GPIO etc)

The IO pins of SoC’s HPS unused or multiplexed on the board have been made available for users with a 40-pin connector to implement extension and customization according to specific applications. Users may easily use QSPI, SPI, I2C, UART and GPIO controllers integrated in HPS.

FPGA Transceiver Extend (Support LVDS, RSDS, SLVS, Mini-LVDS)

The IO pins of SoC’s FPGA unused or multiplexed on the board have been made available for users with a 40-pin connector to implement expansion and customization according to specific applications. Users may easily implement customized high-bandwidth applications running on LVDS, RSDS, SLVS or Mini-LVDS transmission protocol by configuring FPGA’s hardcore and logic resources.

Resources

Embest Lark Board Product Page

Lark Board Quick Start Guide

Lark Board Manual