Introduction

Altera offers an integrated set of System Level Debug (SLD) tools, consisting of:

• SignalTap II Logic Analyzer
• In-System Sources and Probes (ISSP),
• In-System Memory Content Editor)
• Nios II on-chip instrumentation (OCI)

Historically, the Altera System-Level Debugging (SLD) communication solution was based on the Altera JTAG Interface (AJI) which interfaced with the outside world through the JTAG. Then either an USB or Ethernet Blaster could be used to interface JTAG to the host PC.

The new approach is to interface the SLD to the outside world directly through Ethernet, without requiring either an USB or Ethernet Blaster.

You can run a network stack on either a Nios II processor or a Hard Processor System (HPS) and piggyback on an existing remote administration setup. This example project focuses on the case of using an Altera SoC and handling the network stack on the HPS.

Architecture

In the traditional approach the SLD communication solution was based on the Altera JTAG Interface (AJI) which interfaced with the JTAG TAP controller (hard atom in Altera devices which implements the JTAG protocol). The SLD tools used the JTAG channel for communication between software and hardware.

To support communication via TCP/IP, the JTAG TAP controller is replaced by the SLD Hub Controller.

HPS

Altera SoCs integrate an ARM-based hard processor system consisting of a processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. For this application, it is assumed that the HPS in the FPGA is running the Linux Kernel. This simplifies the remote debugging feature. The processor monitors a TCP/IP socket for incoming transactions. The data bytes in these transactions are extracted and written directly to the SLD Hub Controller system hardware without modification. For outgoing data, the SLD Hub Controller system produces data that the processor packages into TCP/IP packets and transmits over the socket without modification.

SLD Hub Controller

The SLD Hub Controller converts Avalon-ST packets to JTAG operations. This component connects most of Altera SLD applications to hardware through a non-JTAG channel (when used together with an appropriate driver in System Console).

Note: You cannot remote debug hardware using a JTAG connection through the JTAG TAP controller after instantiating the SLD Hub Controller component.

SLD Hub

The SLD Hub enables multiple nodes to share access to the user debug interface. The remote debugging feature can support the following system debugging tools over TCP/IP.

• SignalTap II Logic Analyzer
• In-System Sources and Probes
• In-System Memory Content Editor
• Logic Analyzer Interface
• SignalProbe
• System Console

mmlink Application

The mmlink is a Linux application that bridges the SLD Hub Controller to the Ethernet Controller, therefore enabling the SLD Tools to communicate with the Hardware.

System Console

The System Console runs the script mmlink_setup.tcl which enables the remote device being debugged to be seen by the SLD tools.

Instrumenting the Hardware Design

This section explains how to instrumentthe GHRD that is part of the A10 GSRD v15.0.1 in order to support remote debug.

The only modification consists in instantiating the SLD Hub Controller System from Qsys, and connecting its clock, reset and slave port. The slave port needs to be accessible from HPS, and in this example it is connected to the H2F bridge, although it could also be connected to the LWH2F bridge.

For reference, the modified GHRD project is available as part of the deliverables at a10_soc_devkit_ghrd_remotedebug.tar.gz.

Note that the absolute address at which the slave is memory mapped is not important, as the information will be passed from Quartus compilation into the .sopcinfo file, which is the used by the Linux Device Tree Generator to create the Device Tree which is used by Linux driver to determine the location of the component.

Also note that after instrumentation, the hardware project still offers the same functionality as before, except that you cannot use the direct JTAG connection anymore for hardware debugging.

Building Hardware Design, U-Boot and Linux Device Tree

The flow for building the hardware design, U-Boot and the Linux device tree is identical with the one used for A10 GSRD v15.0.1. For reference, here are complete command line instructions:

~/altera/15.0/embedded/embedded_command_shell.sh
cd ~
wget https://releases.rocketboards.org/2015.08/remotedebug/hw/a10_soc_devkit_ghrd_remotedebug.tar.gz
tar xvzf a10_soc_devkit_ghrd_remotedebug.tar.gz
cd a10_soc_devkit_ghrd_remotedebug
make sof
make rbf
make uboot
make dtb

This will create the following items in the folder ~/a10_soc_devkit_ghrd_remotedebug

Item	Description
output_files/ghrd_10as066n2.core.rbf	FPGA fabric configuration file
output_files/ghrd_10as066n2.periph.rbf	FPGA peripheral configuration file
software/bootloader/uboot_w_dtb-mkpimage.bin	Combined U-Boot and U-Boot Device Tree image
ghrd_10as066n2.dtb	Linux Device Tree binary

Building Linux Kernel and Rootfilesystem

The kernel and rootfilesystem are built by using a modified version of the Angstrom recipes that are part of the A10 GSRD v15.0.1.

The modifications are included in the meta-remotedebug layer and consist of the following:

• Add Linux kernel patch that adds the mm-debug-link driver to the Linux kernel
• Add mmlink application that interfaces between SLD Hub and Ethernet connection

Please look at Compiling A10 GSRD v15.0.1 for details on how to setup your host for running Yocto.

The required commands for building the Kernel and rootfilesystem are:

cd ~
wget https://releases.rocketboards.org/2015.08/remotedebug/src/angstrom-socfpga-remotedebug.tar.gz
tar xvzf angstrom-socfpga-remotedebug.tar.gz
cd angstrom-socfpga-remotedebug
MACHINE=arria10 ./oebb.sh config arria10
source ./environment-angstrom-v2014.12
MACHINE=arria10 bitbake virtual/kernel remotedebug-console-image

This will create the following files in the folder ~/angstrom-socfpga-remotedebug/deploy/glibc/images/arria10:

File	Description
remotedebug-console-image-arria10.tar.xz	Rootfilesystem archive
vmlinux	Linux Kernel executable
zImage	Compressed Linux Kernel image

Note that Linux Device Trees are also built, but we are not using them, since we are using the Linux Device Tree built by the Device Tree Generator, in order to include details about the FPGA soft IP peripherals.

Remote Debug Session Example

This section presents an example of how to run a remote debug session.

The following steps are required:

1. Write the include SD card image to an SD card.

2. Boot Linux and login using 'root' as username and no password.

3. Run the following command to start the mmlink application that bridges the SLD Hub to the Ethernet:

/home/root/altera/mmlink

4. Determine the target IP address by looking at the LCD screen or running the following command:

ifconfig

5. On the host PC, download the file https://releases.rocketboards.org/2015.08/remotedebug/src/mmlink_setup.tcl, and run it from an Embedded Command Shell:

system-console -jtag_server --rc_script=./mmlink_setup.tcl ./ghrd_10as066n2.sof ip_of_board 3333

6. Open SignalTap II Logic Analyzer and select SystemConsole on localhost:xxxx under Hardware and Sld Hub Controller System under Device.

7. Use SignalTap II as you would do with a regular/JTAG connection.

Project Deliverables

The deliverables are posted at: https://releases.rocketboards.org/2015.08/remotedebug and consist of the following:

File	Description
remotedebug-15.0.1-a10-bin.tar.gz	Archive containing precompiled binaries
a10_soc_devkit_ghrd_remotedebug.tar.gz	Updated hardware project
angstrom-socfpga-remotedebug.tar.gz	Archive containing Angstrom Yocto recipes
mmlink_setup.tcl	System Console Script

The precompiled binaries archive remotedebug-15.0.1-a10-bin.tar.gz contains the following files:

File	Description
ghrd_10as066n2.core.rbf	FPGA fabric configuration rbf
ghrd_10as066n2.periph.rbf	FPGA peripheral configuration rbf
ghrd_10as066n2.sof	FPGA Configuration file
remotedebug-console-image-arria10.tar.xz	Root filesystem archive
sd_card_remotedebug_a10.img.gz	Compressed bootable SD card image
socfpga_arria10_socdk.dtb	Linux Device Tree binary
uboot_w_dtb-mkpimage.bin	Combined U-Boot and U-Boot Device Tree Image
vmlinux	Linux Kernel executable
zImage	Compressed Linux Kernel image

References

• Design Debugging Using the SignalTap II Logic Analyzer
• Creating a System with Qsys
• Arria 10 Golden System Reference Design v15.01
• Arria 10 SoC Development Kit