Work in Progress: This is a draft document, referring to tools and products that are not yet released!

Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

• ARM Cortex™-A9 MPCore HPS
• Hard Memory Controller (HMC)
• Two user push-button inputs
• Four user DIP switch inputs
• Four user I/O for LED outputs
• 64KB of FPGA on-chip memory
• JTAG to Avalon master bridges
• Interrupt Latency Counter
• System ID

The GHRD allows hardware designers to access each peripheral in the FPGA portion of the SoC with System Console, through the JTAG master module. This signal-level access is independent of the driver readiness of each peripheral.

Cortex-A9 MPU Address Maps

This section presents the address maps as seen from the MPU (Cortex-A9) side.

HPS-to-FPGA Address Map

The memory map of soft IP peripherals, as viewed by the microprocessor unit (MPU) of the Hard Processor System, starts at HPS-to-FPGA base address of 0xC000_0000. The following table lists the offset from 0xC000_0000 of each peripheral in the FPGA portion of the SoC.

Peripheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0	64K	On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The the memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU (Cortex-A9), which starts at the lightweight HPS-to-FPGA base address of 0xFF20_0000, is listed in the following table.

Peripheral	Address Offset	Size (bytes)	Attribute
sysid_qsys	0x0001_0000	8	Unique system ID
led_pio	0x0001_0010	8	LED output display
button_pio	0x0001_0020	8	Push button input
dipsw_pio	0x0001_0030	8	DIP switch input
ILC	0x0001_0100	8	Interrupt latency counter (ILC)

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGAfabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0000_0000	64K	On-chip RAM
sysid_qsys	0x0001_0000	8	Unique system ID
led_pio	0x0001_0010	8	4 LED outputs
button_pio	0x0001_0020	8	2 push button inputs
dipsw_pio	0x0001_0030	8	4 DIP switch inputs
ILC	0x0001_0100	8	Interrupt latency counter (ILC)

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupt connections from soft IP peripherals to the HPS interrupt input interface.

Peripheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0[0]	4 DIP switch inputs
button_pio	f2h_irq0[1]	2 push button inputs

The interrupt sources are also connected to an interrupt latency counter (ILC) module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.