Prerequisites

You will need the following items:

• Arria 10 SoCDevelopment Kit, Rev A or B including:
  • DDR4 Memory Card
  • QSPI Boot Card or SDMMC Boot Card (QSPI Boot setup is used for the pre-compiled example)
• Host PC with:
  • Linux OS - required for compiling U-Boot, which is not supported on Windows
  • Minimum 16GB or RM - required for building the hardware design
  • Serial terminal (for example minicom
  • TFTP Server - for getting Linux binaries to U-Boot to be written to QSPI
  • SoC EDS 15.1b185 - for generating and building U-Boot, and for the A10 GHRD which is used as a starting point
  • ACDS 15.10185 - for compiling the hardware design
• Local Ethernet network, with DHCP server (will be used to provide IP address to the board).

Notes:

• The A10 GHRD design in SoC EDS 15.1.1 and later support the B1 board revision only

Overview

To enable boot from FPGA in the GHRD a number of changes are required:

• The on chip RAM contains a compiled u-boot in .hex format
• The HPS instance includes boot from FPGA signals
• The FPGA top level drives the boot from FPGA signals.

1. Editing the GHRD Hardware Designfor FPGA boot

This section describes how to edit the A10 GHRD to enable the HPS to boot from a bootloader in an FPGA On Chip RAM.

1.1 Editing the Qsys system

The Arria 10 SOC GHRD Qsys System must be edited to add the HPS interfaces for FPGA boot

1. Create a copy of the Arria 10 SOC GHRD design from the SOC EDS installation
2. Open the Arria 10 SOC GHRD system ghrd_10as066n2.qsys in Qsys
3. Edit the Arria 10 Hard Processor System component, and select Enable boot from FPGA signals on the FPGA Interfaces Tab.
4. This adds the f2h_boot_from_fpga conduit connection on the Arria 10 Hard Processor System instance.
5. Export the Arria 10 Hard Processor System f2h_boot_from_fpga conduit by double clicking in the export column in Qsys
6. Confirm that Onchip-memory2_0 is connected to the H2F Bus at address 0x0. This will be used as the boot device
7. Edit Onchip-memory2_0
   1. Confirm that “Initialize memory content” and “Enable non-default initialization file” are selected
   2. Specify the name and path to a user created initialization hex file for the on-chip-ram. Example: /software/hpsBootTarget.hex Note: If only a file name is specified (no path) the Quartus search path will be used to locate the .hex file.
8. Save and generate the Qsys System

1.2 Editing the Arria 10 SOC GHRD Quartus Project

1. Open A10 GHRD project ghrd_10as066n2.qpf in Quartus
2. Ensure the correct device is selected for your development kit: Rev A ES silicon : DEVICE 10AS066N2F40I2SGES Rev B ES2 silicon : DEVICE 10AS066N3F40E2SGE2
3. Edit the top level Verilog in Quartus to add the f2h_boot_from_fpga ports on the ghrd_10as-33n2 Qsys instance, and drive both signals in the f2h_boot_from_fpga conduit to 1.

   .arria10_hps_0_f2h_boot_from_fpga_boot_from_fpga_ready (1'b1),
   .arria10_hps_0_f2h_boot_from_fpga_boot_from_fpga_on_failure (1'b1)

4. An example instantiation template can be generated from the Generate menu in Qsys
5. Enable INIT_DONE output on the Assignments*→*Device*→*Device and Pin Options menu
6. Compile the Design in Quartus

Note

Wait until this has finished before moving to the next step.

2. Boot Loader Generation: u-boot-socfpga

The boot loader must be built and customized to support booting from the FPGA.

1. Open a SoC EDS embedded_command_shell.sh

   % <path>/altera/15.1/embedded/embedded_command_shell.sh

2. Open Bsp-editor

   % bsp-editor

3. Create a new HPS BSP via the File Menu → New HPS BSP
4. Point to the software hand off directory (hps_isw_handoff) created from the Quartus Compile in section 2, and click OK
5. Edit the BSP and select external_fpga_config and boot from SD/MMC or boot from QSPI This compiles in the SD/MMC or QSPI drivers into u-boot, to allow use of the flash in u-boot.
6. Click Generate then Exit
7. Navigate to the location of the created u-boot in your terminal

   % cd <path>/software/<BSP name> 

8. Open the device tree file devicetree.dts in a text editor, and add a config section below the chosen {} section to disable u-boot from loading its environment from a flash device.

   chosen {
      /* Bootloader setting: uboot.external_fpga_config */
      external-fpga-config;
      };
      config {
      load-environment = <0>;
      };

9. Build u-boot by running make, which copies the u-boot-socfpga from the SoCEDS and ARM Development Studio install to bsp directory, and runs a build

   % make 

10. Edit the u-boot configuration file for the Arria 10 SOC to change the text base location of uboot to the base of the on chip RAM on the h2F bridge (0xC000000) Open uboot-socfpga/include/configs/socfpga_arria10.h in a text editor and update as follows

    #ifdef TEST_AT_ASIMOV
       /*#define CONFIG_SYS_TEXT_BASE		0xc0040000*/
       #define CONFIG_SYS_TEXT_BASE		0x10000000
       #else
       /* Update for boot from FPGA */
       /*#define CONFIG_SYS_TEXT_BASE		0xFFE00000*/
       #define CONFIG_SYS_TEXT_BASE		0xC0000000
       /* Update for boot from FPGA END */
       #endif
       

11. Edit the u-boot configuration file for the Arria 10 SOC to set the MAC address for the Ethernet IP in the default environment. Open uboot-socfpga/include/configs/socfpga_arria10.h in a text editor to add an entry for ethaddr as follows. Replace <XX:XX:XX:XX:XX:XX> with a with a 12 character hex string of the format XX:XX:XX:XX:XX:XX

    #define CONFIG_EXTRA_ENV_SETTINGS \
    	"verify=y\0" \
    	"ethaddr=<XX:XX:XX:XX:XX:XX>\0" \
    	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \   

12. Edit u-boot header file for Arria 10 to disable NOC security and privilege restrictions to allow access to the FPGA on chip RAM Open <path>/software/<BSP Name>/uboot-socfpga/board/altera/socfpga_arria10/socfpga_common.c in a text editor Add the code to the int board_init function as follows:

    int board_init(void)
       {
       /* address of boot parameters for ATAG (if ATAG is used) */
       gd->bd->bi_boot_params = 0x00000100;
    
       /*code additions start*/
       /* Disable security / privilege in the A10 NOC to allow masters to write to FPGA OCM */
       writel(0x03fe0101, 0xFFD13500);
       //noc_fw_soc2fpga_soc2fpga_scr:lwsoc2fpga: Allow unsecured accesses from all masters When cleared (0) secure access only
       writel(0x03fe0101, 0xFFD13504);
       //noc_fw_soc2fpga_soc2fpga_scr:soc2fpga: Allow unsecured accesses from all masters When cleared (0) secure access only
       writel(0xffffffff, 0xFFD11004);
       //noc_l4_priv_l4_priv_filter: Allow all peripherals to accept non privileged accesses. (When cleared (0) only privileged access are allowed)
       /*code additions end*/
    
       return 0;
       }

13. Optional: Apply patch to u-boot to enable saving of environment data to the QSPI

    % cd <path>/software/<BSP name>/uboot-socfpga
       % git apply 0001-FogBugz-299119-Enable-U-Boot-environment-in-QSPI.patch
       

14. Re-build u-boot

    % cd <path>/software/<BSP name>/
       % make clean
       % make

15. Convert the generated preloader image uboot_w_dtb-mkpimage.bin to Intel .hex format for loading into the FPGA on chip RAM.

    % arm-altera-eabi-objcopy -I binary -O ihex --adjust-vma -0x00000000 u-boot_w_dtb.bin hpsBootTarget.hex

3. Updating the Qsys project

The Qsys project must be updated to specify the hpsBootTarget.hex file as the initial content for the on Chip RAM

1. Open the Arria 10 SOC GHRD system in Qsys
2. Edit Onchip-memory2_0 in Qsys, and select the .hex file created in 2.14 as initialization source.
3. Regenerate the Qsys System
4. Re-compile the Arria 10 SOC GHRD Quartus Project

Note: The Quartus MIF update flow can be used to update the content of an on chip RAM.

4. Optional: MIF Update Flow

The MIF Update Flow can be used to update the content of an FPGA On Chip RAM without running a full compile in Quartus. The name and location of the .hex file must be as specified when the Qsys system was created (or if no path was specified for the .hex file the name bust be correct, and the .hex file location must be on the Quartus Search Path).

1. Copy your generated .hex file to the Quartus project directory
2. From the commaTnd line run

   % quartus_cdb  -c  --update_mif
      % quartus_cdb ghrd_10as066n2 -c ghrd_10as066n2 --update_mif 

3. Re-run the Assember

   %quartus_asm --read_settings_files=on --write_settings_files=off  -c 
      %quartus_asm --read_settings_files=on --write_settings_files=off ghrd_10as066n2 -c ghrd_10as066n2 

5. Optional: Convert the programming file to RBF format

The programming file can be converted to RBF format for use on flash devices

 %quartus_cpf -c -o bitstream_compression=on ghrd_10as066n2.sof ghrd_10as066n2.rbf 

6. Configuring the board for FPGA Boot

1. Ensure you have a UART terminal connected to the board to see output messages
2. Set up BSEL pins to correct value

• SDMMC Flash board
  • Set the BSEL [2:0} pins to the correct value using the SDMMC rev B daughter board:

     BSEL[2:0] settings:
    
             Boot from FPGA	0x1
             Boot from SDMMC	0x4 
    
             BSEL2	BSEL1	BSEL0   
             J5	J4	J3
             0     	0	1  	Boot from FPGA 
             1     	0	0  	SD/MMC flash memory 
    
             Pin 3 is marked on jumpers 3-5.  If pin 3 is shorted this is = “0”

Note

Rev A SDMMC daughter board do not have jumpers for BSEL, the HPS will fall back to boot from FPGA if no bootloader is found.

• QSPI Flash Board
  • If the QSPI flash board is mounted on the boot flash header, BSEL will be set to boot from QSPI.
  • If the QSPI does not contain a valid bootloader the HPS will boot from FPGA as fall back.
  • A u-boot image can erased from QSPI via u-boot:

    sf probe
    sf erase 0x0 1024000 

7. Test the system

1. Power on the board and connect the UART
2. Program the A10 FPGA via JTAG with the .sof created in section 3 using Quartus Programmer.

Once FPGA programming completes, the HPS should boot to u-boot

Known limitations (being debugged)

• Reset of HPS: If the HPS is reset the FPGA must be re-programmed
• Access to the SDMMC flash controller in SD Mode fails when the u-boot is executed from the FPGA on-chip-ram.
  • This is a software bug and debug is on going
  • EMMC mode work
  • The QSPI Controller is not affected by this problem

• 0001-FogBugz-299119-Enable-U-Boot-environment-in-QSPI.patch