Compiling Hardware Design

Overview

This page presents how to re-compile the hardware design that comes with SoC EDS 18.0 and beyond. This may be needed in case any changes are made to the design. Otherwise the pre-compiled design can be used as-is.

Prerequisites

The following items are required:

• Host PC running Linux (CentOS 6.8 or Ubuntu 14.04LTS)
• Quartus™ Prime and GHRD Archive according to Release Tags.

Compiling Hardware Design

1. Retrieve the archive file a10_soc_devkit_ghrd.tar.gz corresponding to your board, containing the hardware design and save it in the home folder.

Refer to Release Contents for the tarball to download according to the releases and board you need and download the design which you need for example for GHRD the design is a10_soc_devkit_ghrd.tar.gz

2. Extract the files from the archive

$ cd ~
$ tar xzf a10_soc_devkit_ghrd.tar.gz

3. Start Quartus Prime

$ ~/intelFPGA/19.3/quartus/bin/quartus --64bit

4. In Quartus open the hardware project by going to File → Open Project ... Then browse to ~a10_soc_devkit_ghrd/ghrd_10as066n2.qpf and click Open.

5. In Quartus, start Platform Designer by going to Tools → Platform Designer.

6. The tool will ask to select a file to open. Select the file ~/a10_soc_devkit_ghrd/ghrd_10as066n2.qsys and click Open.

7. Platform Designer will load the file, displaying a progress bar. Once file is loaded, Platform Designer will display the system.

8. In Platform Designer, click the "Sync All System Infos", then "Validate System Integrity" and "Reload and Update All Components" to refresh the IP. Then click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.

9. Platform Designer will generate the system, displaying a progress bar.

10. Once complete, Platform Designer will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Platform Designer window.

11. Click Finish to close the Platform Designer window and get back to main Quartus window.

12. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project

13. When compilation is completed, Quartus will display the status.

The following will be created:

• ~/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof - FPGA configuration file
• ~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree

Convert Programming File

The sof file produced by compiling the hardware design needs to be converted to the rbf format required by the U-Boot. It is also split into two different files:

• peripheral file - for configuring the IO ring
• core file - for configuring the FPGA fabric

The required steps are:

1. Start an embedded command shell

$ ~/intelFPGA/19.3/embedded/embedded_command_shell.sh

2. Go to the GHRD folder

$ cd ~/a10_soc_devkit_ghrd/

3. Convert the file

For Rev C board:

$ quartus_cpf -c --hps -o bitstream_compression=on output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbf

This will create the following file in the ~/a10_soc_devkit_ghrd/output_files/ folder:

• ghrd_10as066n2.periph.rbf - IO ring configuration file
• ghrd_10as066n2.core.rbf - FPGA fabric configuration file