RocketBoards- Home
- Documentation
- Community
- Projects
- Boards
- Agilex 5 SoC
- Agilex 7 SoC
- Arria 10 SoC
- Nallatech 385A - Arria 10 FPGA Network Accelerator Card
- Nallatech 385A-SoC Accelerator Card with Arria 10 FPGA
- ALARIC Instant DevKit ARRIA 10 SoC FMC IDK by REFLEX CES
- Altera Arria 10 SoC Virtual Platform
- Altera Arria 10 SoC Board
- Nallatech 510T compute acceleration card with Intel Arria 10 FPGA
- REFLEX CES Achilles Arria 10 SoC SOM
- Terasic Arria10 SoC Board : HAN Pilot Platform
- Arria V SoC
- Cyclone V SoC
- Altera Cyclone V SoC Board
- Arrow SoCKit User Manual - July 2017 Edition
- Arrow SoCKit User Manual - November 2019 Edition
- Arrow SoCKit Evaluation Board
- Atlas-SoC Development Platform
- Critical Link MitySOM-5CSx Development Kit
- Cyclone V Ethernet driver problems
- DE10-Nano Development Board
- Terasic DE10-Standard Development Kit
- Devboards DBM-SoC1 module
- Devboards DBM-SoC2 module
- EBV SoCrates Evaluation Board
- Enclustra Mercury SA1 SoC Module
- Enterpoint Drigmorn 5
- Enterpoint Larg 2
- Altera Cyclone V SoC Development Platform
- Mpression Helio SoC Evaluation Kit by Macnica
- Mpression Sodia Evaluation Board by Macnica
- ARIES Embedded - MCV System on Module
- Mpression Borax SOM Module and Development Kit by Macnica
- Enterpoint Mulldonoch 3
- Networked Pro-Audio FPGA SoC Development Kit by Coveloz
- NOVPEK™CVLite
- NOVSOM®CV
- NOVSOM®CVLite
- NovTech IoT Octopus™
- NovTech NetLeap™
- Enterpoint Raggedstone 4
- Solectrix SMARC compliant System-on-Module
- Terasic DE1-SoC Development and Education Board
- Stratix 10 SoC
- Find a Board
- News
Compiling Hardware Design How to re-compile the hardware design
Configuration
Board(s):
Altera Arria 10 SoC BoardTools Version(s):
15.0.1- Select a different Task
Recent Changes
-
Remote FPGA Debug for Agilex 7
Remote FPGA Debug over Ethernet for Agilex 7
-
GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile)
Golden System Reference Design for DK SI AGF014EA -
Application Development with Yocto eSDK
Using Yocto Extensible SDK for Application Development -
GHRD for Agilex 5 FPGA E-Series 065B Premium Development Kit
Golden Hardware Reference Design for DK A5E065BB32AES1 -
Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices
This page needs tagging. Please add keywords describing what this page is about.
Overview
This page presents how to re-compile the hardware design that comes with <nop>SoC EDS 15.0. This may be needed in case any changes are made to the design. Otherwise the pre-compiled design can be used as-is.Prerequisites
The following items are required:- Host PC running Linux (CentOS 6.5 or Ubuntu 12.04LTS)
- Altera Quartus™ II v15.0 - http://www.altera.com/products/software/sfw-index.jsp
- GHRD v15.0.1 Archive from https://releases.rocketboards.org/2015.06/gsrd/hw
Compiling Hardware Design
1. Retrieve and the archive file a10_soc_devkit_ghrd.tar.gz containing the hardware design and save it in the home folder. The file is available at https://releases.rocketboards.org/2015.06/gsrd/hw. 2. Extract the files from the archive$ cd ~ $ tar xzf a10_soc_devkit_ghrd.tar.gz3. Start Quartus II
$ ~/altera/15.0/quartus/bin/quartus --64bit
4. In Quartus open the hardware project by going to File → Open Project ... Then browse to ~a10_soc_devkit_ghrd/ghrd_10as066n2.qpf and click Open.
5. In Quartus, start Qsys by going to Tools → Qsys.
6. The tool will ask to select a file to open. Select the file ~/a10_soc_devkit_ghrd/ghrd_10as066n2.qsys and click Open.
7. QSys will load the file, displaying a progress bar. Once file is loaded, Qsys will display the system.
8. In Qsys, click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.
9. Qsys will generate the system, displaying a progress bar.
10. Once complete, Qsys will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Qsys window.
11. Click Finish to close the Qsys window and get back to main Quartus window.
12. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project
13. When compilation is completed, Quartus will display the status.
The following will be created: - ~/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof - FPGA configuration file
- ~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree
Convert Programming File
The sof file produced by compiling the hardware design needs to be converted to the rbf format required by the U-Boot. It is also split into two different files:- peripheral file - for configuring the IO ring
- core file - for configuring the FPGA fabric
$ ~/altera/15.0/embedded/embedded_command_shell.sh2. Go to the GHRD folder
$ cd ~/a10_soc_devkit_ghrd/3. Convert the file
$ quartus_cpf -c --hps -o bitstream_compression=on output_files/ghrd_10as066n2.sof output_files/ghrd_10as066n2.rbfThis will create the following files in the ~/a10_soc_devkit_ghrd/output_files/ folder:
- ghrd_10as066n2.periph.rbf - IO ring configuration file
- ghrd_10as066n2.core.rbf - FPGA fabric configuration file
© 1999-2024 RocketBoards.org by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
This website is using cookies. More info.
That's Fine