Introduction
The GSRD (Golden System Reference Design) provides a set of essential hardware and software system components that can be used as a starting point for various custom user designs.
Getting Started Guides
GSRD Overview
The A10 GSRD consists of:
- Arria 10 SoC Development Board rev.A
- Golden Hardware Reference Design (GHRD)
- Linux release
- Linux sample drivers
- Linux sample applications
Release Notes
See
Release Notes.
Release Contents
See
Release Contents.
Release Location
The A10 GSRD v15.0.1 Release is available at
https://releases.rocketboards.org/2015.06.
Prerequisites
The following are required in order to be able to fully exercise the A10 GSRD:
- Arria 10 SoC Development Board rev.A
- Host PC running Linux (CentOS 6.6 was tested to work)
- Altera Arria 10 SoC Development Board
- Altera SoC EDS v15.0.1b60
- Altera Quartus™ II v15.0b145
Note that the Bootloader (U-Boot) compilation requires a Linux host PC. The rest of the operations can be performed on a Windows host PC also.
Default Paths
Throughout the documentation, the following default paths are assumed. Please update the commands accordingly if non-standard paths are used.
| Default Path |
Description |
|---|
| ~/altera/15.0/embedded |
SoC EDS installation path |
| ~/altera/15.0/qprogrammer |
Quartus II Programmer installation path |
| ~/altera/15.0/quartus |
Quartus II installation path |
| ~/a10_soc_devkit_ghrd |
Arria 10 GHRD folder, copied from SoC EDS installation path: ~/altera/15.0/embedded/examples/hardware |
GHRD Overview
See
GHRD Overview.
Build Flow
The following diagram illustrates the full build flow for the GSRD.
Important Note: As shown above, on Arria 10 there are two different Device Trees: the one required by Bootloader (U-Boot), and another one required by the Linux Kernel.
The following table presents the tools that are used in the build flow:
| Tool |
Description |
Part of |
|---|
| Quartus II |
Create, edit and compile FPGA hardware designs |
ACDS |
| Quartus Programmer CPF |
Utility that converts FPGA programming file from SOF to RBF format |
^ |
| Linux Device Tree Generator |
Generate Device Trees for Linux |
SoC EDS |
| dtc |
Device Tree Compiler, converts device tree source file to binary format (blob) |
^ |
| Bootloader Generator |
Generates Bootloader device tree and makefile based on hardware handoff information |
^ |
| ARM DS-5 AE |
Software Development Suite |
^ |
The following table presents the input files that are part of the build process:
| File |
Description |
|---|
| GHRD |
Quartus Project - FPGA Hardware Project source code |
| Board XML Files |
File describing the development board, used in creating the Device Tree |
| Linux Root Filesystem |
Prebuilt Linux root filesystem |
The following table describes the rest of the items that are part of the build flow diagram:
| File |
Description |
|---|
| .sof |
SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project |
| .rbf |
Raw Binary File - Compressed FPGA programing file |
| .sopcinfo |
SOPC Info File - containing a description of the hardware to be used by Device Tree Generator |
| Handoff Folder |
Folder containing a description of the hardware to be used by the Bootloader Generator, in XML format |
Not all the people involved in a project need to deal with the full flow. For example:
- Board Designer: Typically works with the hardware engineer to decide the design of the custom board, pin muxing, and to update the Board XML file used by the Device Tree Generator.
- Hardware Engineer: Usually works only on the FPGA Quartus Project, and notifies the firmware engineer whenever the hardware files (.sof, .rbf, .sopcinfo, handoff folder) were changed. He also needs to notify the firmware engineer of any hardware interface changes.
- Firmware Engineer: Typically updates the Linux drivers according to the changes that were performed in hardware, recompiles the kernel if necessary. Re-generates the Device Tree when needed.
- Software Engineer: Develops the applications that run on top of the Linux OS. May need to change the software when new drivers are added.
HPS Boot Flow
The
Golden System Reference Design (GSRD) User Manuals boot flow includes the following stages:
- BootROM
- U-Boot
- Linux
The following table presents a short description of the different boot stages:
| Stage |
Description |
|---|
| BootROM |
Performs minimal configuration and loads U-Boot into 256KB OCRAM |
| U-boot |
Configures IO, FPGA, brings up DDRAM, loads Linux kernel |
| Linux |
Runs the end application |
For more information about Arria 10 SoC booting please refer to
Arria 10 Hard Processor System Technical Reference Manual, Booting and Configuration chapter.
Linux Documentation
See
Linux BSP User Manual.
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