Introduction

The Arria 10 Triple Speed Ethernet (TSE) reference design provides a set of essential hardware and software system components that can be used as a starting point for various custom user designs.

Getting Started Guides

• Compiling the Hardware Design
• Generating U-Boot and U-Boot Device Tree
• Generating the Linux Device Tree
• Compiling Linux Kernel and Root Filesystem
• Creating and Updating the SD Card
• Booting Linux Using SD Card Image
• Exercising TSE interfaces

Triple Speed Ethernet Overview

The A10 Triple Speed Ethernet Reference Design consists of:

• Arria 10 SoC Development Board Rev C
• Triple Speed Ethernet Hardware Reference Design
• Linux release

Release Location

The A10 Triple Speed Ethernet v18.1. The hardware design release is available at HERE

For full sdimage create please refer to HERE

Prerequisites

The following are required in order to be able to fully exercise the A10 Triple Speed Ethernet RD:

• Host PC running Linux (CentOS 6.8 was tested to work)
• Intel Arria 10 SoC Development Board Rev C
• Intel SoC EDS v18.1
• Intel Quartus™ Prime Pro v18.1

Note that the Bootloader (U-Boot) compilation requires a Linux host PC. The rest of the operations can be performed on a Windows host PC also.

Default Paths

Throughout the documentation, the following default paths are assumed. Please update the commands accordingly if non-standard paths are used.

Default Path	Description
~/intelFPGA_pro/18.1 /embedded	SoC EDS installation path
~/intelFPGA_pro/18.1 /qprogrammer	Quartus Prime Pro Programmer installation path
~/intelFPGA_pro/18.1 /quartus	Quartus Prime Pro installation path
~/a10_soc_devkit_tse	Arria 10 hardware RD folder

Triple Speed Ethernet hardware design Overview

See Triple Speed Ethernet RD Overview.

Build Flow

The following diagram illustrates the full build flow for the Triple Speed Ethernet RD.

Important Note: As shown above, on Arria 10 there are two different Device Trees: the one required by Bootloader (U-Boot), and another one required by the Linux Kernel.

The following table presents the tools that are used in the build flow:

Tool	Description	Part of
Quartus Programmer	Create, edit and compile FPGA hardware designs	ACDS
Quartus Programmer CPF	Utility that converts FPGA programming file from SOF to RBF format	^
Linux Device Tree Generator	Generate Device Trees for Linux	SoC EDS
dtc	Device Tree Compiler, converts device tree source file to binary format (blob)	^
Bootloader Generator	Generates Bootloader device tree and makefile based on hardware handoff information	^
ARM DS-5 AE	Software Development Suite	^

The following table presents the input files that are part of the build process:

File	Description
GHRD	Quartus Project - FPGA Hardware Project source code
Board XML Files	File describing the development board, used in creating the Device Tree
Linux Root Filesystem	Prebuilt Linux root filesystem

The following table describes the rest of the items that are part of the build flow diagram:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.rbf	Raw Binary File - Compressed FPGA programing file
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
Handoff Folder	Folder containing a description of the hardware to be used by the Bootloader Generator, in XML format

Not all the people involved in a project need to deal with the full flow. For example:

• Board Designer: Typically works with the hardware engineer to decide the design of the custom board, pin muxing, and to update the Board XML file used by the Device Tree Generator.
• Hardware Engineer: Usually works only on the FPGA Quartus Project, and notifies the firmware engineer whenever the hardware files (.sof, .rbf, .sopcinfo, handoff folder) were changed. He also needs to notify the firmware engineer of any hardware interface changes.
• Firmware Engineer: Typically updates the Linux drivers according to the changes that were performed in hardware, recompiles the kernel if necessary. Re-generates the Device Tree when needed.
• Software Engineer: Develops the applications that run on top of the Linux OS. May need to change the software when new drivers are added.

HPS Boot Flow

The Triple Speed Ethernet RD boot flow includes the following stages:

1. BootROM
2. U-Boot
3. Linux

The following table presents a short description of the different boot stages:

Stage	Description
BootROM	Performs minimal configuration and loads U-Boot into 256KB OCRAM
U-boot	Configures IO, FPGA, brings up DDRAM, loads Linux kernel
Linux	Runs the end application

For more information about Arria 10 SoC booting please refer to Arria 10 Hard Processor System Technical Reference Manual, Booting and Configuration chapter.