Introduction

The GSRD (Golden System Reference Design) provides a set of essential hardware and software system components that can be used as a starting point for various custom user designs.

Getting Started Guides

Cyclone V Getting Started Guides

• Compiling the Hardware Design
• Generating and Compiling the Preloader
• Generating the Device Tree
• Compiling Angstrom Linux Distribution
• GSRD FPGA Programming
• Creating and Updating SD Card
• FPGA Programming with Quartus Prime Standard Programmer
• Angstrom Getting Started
• Booting Linux from SD Card Image
• Connecting to Board Web Server
• Connecting to Board Using SSH
• Running Sample Linux Applications

Arria V Getting Started Guides

• Compiling the Hardware Design
• Generating and Compiling the Preloader
• Generating the Device Tree
• Compiling Angstrom Linux Distribution
• GSRD FPGA Programming
• Creating and Updating SD Card
• FPGA Programming with Quartus Prime Standard Programmer
• Angstrom Getting Started
• Booting Linux Using Prebuilt SD Card Image
• Connecting to Board Web Server
• Connecting to Board Using SSH
• Running Sample Linux Applications

GSRD Overview

The GSRD consists of:

• Cyclone V SoC Development Board or Arria V SoC Development Board
• Golden Hardware Reference Design (GHRD)
• Linux release
• Linux sample drivers
• Linux sample applications
• Web server running on target board

Release Notes, Release Contents, Locations and Release Tags

The latest release notes, contents and tags can be found here:

Release Notes, Contents, Locations and Tags

Prerequisites

The following are required in order to be able to fully exercise the GSRD:

• Host PC running Linux (Ubuntu 14.04LTS were tested to work)
• Cyclone V SoC Development Board rev. E or Arria V SoC Development Board rev. C
• Intel SoC EDS v17.1 - available from http://www.altera.com/products/software/sfw-index.jsp
• Intel Quartus™ II v17.1 - available from http://www.altera.com/products/software/sfw-index.jsp

Default Paths

Throughout the documentation, the following default paths are assumed. Please update the commands accordingly if non-standard paths are used.

Default Path	Description
~/intelFPGA/embedded	SoC EDS installation path
~/intelFPGA/qprogrammer	Quartus II Programmer installation path
~/intelFPGA/quartus	Quartus II installation path
~/cv_soc_devkit_ghrd	Cyclone V GHRD folder, extracted from cv_soc_devkit_ghrd.tar.gz
~/av_soc_devkit_ghrd	Arria V GHRD folder, extracted from av_soc_devkit_ghrd.tar.gz

GHRD Overview

See GHRD Overview.

HPS Boot Flow

See HPS Boot Flow.

Development Flow Overview

The following picture presents a high level view of the development flow for projects based on the GSRD.

Detailed GSRD Build Flow

The following diagram illustrates the full build flow for the GSRD.

The following table presents the tools that are used in the build flow:

Tool	Description	Part of
Quartus II	Create, edit and compile FPGA hardware designs	ACDS
Device Tree Generator	Generate Device Trees	SoC EDS
Device Tree Compiler	Converts between Device Tree file formats	^
Preloader Generator	Generates Preloader source code based on hardware handoff information	^
ARM DS-5 AE	Software Development Suite	^
Bitbake	Yocto build utility	Yocto Source Package
SD Card Script	Script that creates the SD card image	^

The following table presents the input files that are part of the build process:

File	Description
Quartus Project	FPGA Hardware Project source code
Board XML Files	File describing the development board, used in creating the Device Tree
Yocto Recipes	Yocto recipes for building the Linux deliverables
Web Server Files	Additional files needed for the web server running on the board

The following table describes the rest of the items that are part of the build flow diagram:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.rbf	Raw Binary File - Compressed FPGA programing file
.dts	Device Tree Source - used to describe the hardware for the Linux kernel
.dtb	Device Tree Binary - binary representation of the .dts
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svd	System View Description File - describes the hardware for the DS-5 debugger
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

Not all the people involved in a project need to deal with the full flow. For example:

• Board Designer: Typically works with the hardware engineer to decide the design of the custom board, pin muxing, and to update the Board XML file used by the Device Tree Generator.
• Hardware Engineer: Usually works only on the FPGA Quartus Project, and notifies the firmware engineer whenever the hardware files (.sof, .rbf, .sopcinfo, handoff folder) were changed. He also needs to notify the firmware engineer of any hardware interface changes.
• Firmware Engineer: Typically updates the Linux drivers according to the changes that were performed in hardware, recompiles the kernel if necessary. Re-generates the Device Tree when needed.
• Software Engineer: Develops the applications that run on top of the Linux OS. May need to change the software when new drivers are added.

Linux Documentation

• Linux BSP User Manual
• Device Tree Generator User Guide