Compiling Hardware Design

How to compile the FPGA Hardware design that is delivered as part of the GSRD release

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Overview

The compilation will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svd	System View Description File - describes the hardware for the DS-5 debugger
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

Prerequisites

The following items are required:

• Host PC running Linux (CentOS 6.8 or Ubuntu 14.04LTS)
• Intel FPGA Quartus - http://www.altera.com/products/software/sfw-index.jsp, supported releases:

  16.1

  17.0std

  17.1std

  18.0std

  18.1std

• GHRD Archive from https://releases.rocketboards.org/

Procedure

The procedure described below uses the Arria V GHRD. The procedure for Cyclone V GHRD is similar, with only the file names being changed: Download links for the hardware design could be acquired from Release Contents

Open Quartus Project

1. Retrieve and the archive file av_soc_devkit_ghrd.tar.gz containing the hardware design from Release Contents and save it in the home folder.

2. Extract the files from the archive

$ cd ~
$ tar xzf av_soc_devkit_ghrd.tar.gz

3. Make all the files writable (optional)

$ chmod +w -R ~/av_soc_devkit_ghrd/

4. Start Quartus tool by double clicking the icon on the desktop, or by running it from the command line:

$ ~/intelFPGA/[ACDS version]/quartus/bin/quartus --64bit 

5. In Quartus, go to File → Open Project ..., browse to the file ~/av_soc_devkit_ghrd/ghrd_5astfd5k3.qpf and click Open.

6. Quartus will load the project.

Generate System in Platform Designer

7. In Quartus, go to Tools → Platform Designer to start the Platform Designer tool

8. Platform Designer tool will start and ask you to open a qsys file. Select ~/av_soc_devkit_ghrd/ghrd_5astfd5k3.qsys and click Open.

9. Platform Designer will load the file

10. In Platform Designer, select Generate → Generate HDL.. this will open the Generate dialogue box.

11. In the Generate dialogue box, click the Generate button.

12. A message will be displayed when the generation is complete (may take a few minutes depending on host machine speed)

13. Click Close button in the Generation window to close it.

14. In Platform Designer, go to File → Exit to close Platform Designer.

Compile the Design in Quartus

Running Analysis & Synthesis

15. In Quartus, in the Tasks panel change the flow from RTL Simulation to Compilation.

Running the Assembler

17. In the Tasks panel, select Assembler, right click it and select Start.

18. After the assembly phase is completed, a notification message will be displayed.

Generated Files

This section presents the name and location of the files resulted from compiling the hardware design.

CycloneV contents

File	Description
~/cv_soc_devkit_ghrd/output_files/soc_system.sof	SRAM Object File - for programming FPGA
~/cv_soc_devkit_ghrd/soc_system.sopcinfo	SOPC Info File - Used by Device Tree Generator
~/cv_soc_devkit_ghrd/soc_system/synthesis/soc_system_hps_0_hps.svd	System View File - Used by ARM DS-5 AE
~/cv_soc_devkit_ghrd/hps_isw_handoff	Handoff folder - Used by Preloader Generator

ArriaV contents

File	Description
~/av_soc_devkit_ghrd/output_files/ghrd_5astfd5k3.sof	SRAM Object File - for programming FPGA
~/av_soc_devkit_ghrd/ghrd_5astfd5k3.sopcinfo	SOPC Info File - Used by Device Tree Generator
~/av_soc_devkit_ghrd/soc_system/synthesis/ghrd_5astfd5k3_hps_0_hps.svd	System View File - Used by ARM DS-5 AE
~/av_soc_devkit_ghrd/hps_isw_handoff	Handoff folder - Used by Preloader Generator

#ConvertRbf

Converting .sof to .rbf

The SOF (SRAM Object File) file can use used to program the FPGA from the Quartus Programmer tool.

However, for the purpose of programming the FPGA from software, the SOF file needs to be converted to a RBF (Raw Binary File) format.

Several different options are available for converting the file:

A. Using the command line tools from Quartus Programmer (installed by default with the SoCEDS and ARM Development Studio or installed standalone) or from Quartus.

 $ ~/intelFPGA/[acds version]/quartus/bin/quartus_cpf -c \
  ~/av_soc_devkit_ghrd/output_files/ghrd_5astfd5k3.sof  \
  ~/av_soc_devkit_ghrd/output_files/ghrd_5astfd5k3.rbf 

B. Using the GUI converter, callable from either Quartus Programmer or Quartus by selecting the menu File → Convert Programming Files.

1. Select the Programming File Type to be Raw Binary File (.rbf)
2. Select the Mode to be Fast Passive Parallel X8 or 16
3. Click on the SOF Data then click Add File and browse to the ghrd_5astfd5k3.sof file
4. Edit the desired name of the output file to be soc_system.rbf
5. Click the Generate button