RocketBoards- Home
- Documentation
- Community
- Projects
- Boards
- Agilex 5 SoC
- Agilex 7 SoC
- Arria 10 SoC
- Nallatech 385A - Arria 10 FPGA Network Accelerator Card
- Nallatech 385A-SoC Accelerator Card with Arria 10 FPGA
- ALARIC Instant DevKit ARRIA 10 SoC FMC IDK by REFLEX CES
- Altera Arria 10 SoC Virtual Platform
- Altera Arria 10 SoC Board
- Nallatech 510T compute acceleration card with Intel Arria 10 FPGA
- REFLEX CES Achilles Arria 10 SoC SOM
- Terasic Arria10 SoC Board : HAN Pilot Platform
- Arria V SoC
- Cyclone V SoC
- Altera Cyclone V SoC Board
- Arrow SoCKit User Manual - July 2017 Edition
- Arrow SoCKit User Manual - November 2019 Edition
- Arrow SoCKit Evaluation Board
- Atlas-SoC Development Platform
- Critical Link MitySOM-5CSx Development Kit
- Cyclone V Ethernet driver problems
- DE10-Nano Development Board
- Terasic DE10-Standard Development Kit
- Devboards DBM-SoC1 module
- Devboards DBM-SoC2 module
- EBV SoCrates Evaluation Board
- Enclustra Mercury SA1 SoC Module
- Enterpoint Drigmorn 5
- Enterpoint Larg 2
- Altera Cyclone V SoC Development Platform
- Mpression Helio SoC Evaluation Kit by Macnica
- Mpression Sodia Evaluation Board by Macnica
- ARIES Embedded - MCV System on Module
- Mpression Borax SOM Module and Development Kit by Macnica
- Enterpoint Mulldonoch 3
- Networked Pro-Audio FPGA SoC Development Kit by Coveloz
- NOVPEK™CVLite
- NOVSOM®CV
- NOVSOM®CVLite
- NovTech IoT Octopus™
- NovTech NetLeap™
- Enterpoint Raggedstone 4
- Solectrix SMARC compliant System-on-Module
- Terasic DE1-SoC Development and Education Board
- Stratix 10 SoC
- Find a Board
- News
Documentation
Recent Changes
-
GHRD for Agilex 5 FPGA E-Series 065B Premium Development Kit
Golden Hardware Reference Design for DK A5E065BB32AES1 -
Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices -
Docker Yocto Build
Using Docker to Build Yocto Recipes
-
Building Bootloader for Agilex 7
Building latest bootloaders for Agilex 7 SoC Devices -
Intel Agilex® 7 FPGA I-Series PCIe Root Port Reference Design
Demonstrates a PCIe root port running on Agilex 7 SoC Development Kit
Table of Contents
How to generate and compile the Preloader, based on the handoff information from Quartus.
How to generate and compile the Preloader, based on the handoff information from Quartus.
Overview
Note: It is highly recommended preloader and u-boot are built from the same commit.
Prerequisites
The following are required in order to be able to fully exercise the Golden System Reference Design (GSRD) User Manuals:- Host PC running Linux (CentOS 6.8 or Ubuntu 14.04LTS)
- Intel SoC EDS from http://www.altera.com/products/software/sfw-index.jsp
- GHRD Release- from
Reference Information
For detailed information about the Preloader Generator see SoC EDS User GuideProcedure
The procedure shown below uses the Cyclone V GHRD as an example. The procedure for Arria V GHRD is identical, with only file names being changed.Generating the Preloader
1. Compile the GHRD as described in Compiling the Hardware Design to obtain the handoff folder. 2. Start an Embedded Command Shell and go to GHRD folder (assumed here to be saved in the home folder):$ ~/intelFPGA/[acds_version]/embedded/embedded_command_shell.sh $ cd ~/cv_soc_devkit_ghrd3. Start the Preloader Generator aka BSP Editor
$ bsp-editor&4. In the BSP Editor, select File → New BSP ...
5. In the New BSP window, click the ... browse button to browse to the handoff folder
6. Select the cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 folder and Click Open.
7. The New BSP window will have all the settings populated, based on the handoff folder. Accept the default settings and click OK. This will close the window.
8. In the BSP Editor window, edit any settings if necessary, then click Generate.
9. The message panel on the bottom will indicate the status of the generation. Click Exit to close the BSP Editor.
The following items are generated in the cv_soc_devkit_ghrd/software/spl_bsp/ folder | File | Description |
|---|---|
| generated | Folder containing source code that was generated based on the information from the handoff folder |
| settings.bsp | Preloader settings file, that contains the settings from the Preloader Generator |
| Makefile | Makefile used to build the Preloader |
| preloader.ds | ARM DS-5 AE that can be used to load the Preloader |
Compiling the Preloader
1. Start an Embedded Command Shell and go to the generated Preloader folder:$ ~/intelFPGA/[acds_version]/embedded/embedded_command_shell.sh $ cd ~/cv_soc_devkit_ghrd/software/spl_bsp2. Run makecommand to build the Preloader image
$ makeThe Makefile (also created by the Preloader Generator) performs the following steps:
- Extract the fixed part of the Preloader source code
- Build the Preloader executable using the fixed and the generated parts of the Preloader source code
- Convert the executable to binary, then add the bootROM required header on top of it
| File | Description |
|---|---|
| uboot-socfpga/spl/u-boot-spl | Preloader ELF file |
| uboot-socfpga/spl/u-boot-spl.bin | Preloader binary file |
| preloader-mkpimage.bin | Preloader image with the BootROM required header |
© 1999-2024 RocketBoards.org by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
This website is using cookies. More info.
That's Fine