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- Arrow SoCKit User Manual - July 2017 Edition
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- Enterpoint Drigmorn 5
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- Mpression Helio SoC Evaluation Kit by Macnica
- Mpression Sodia Evaluation Board by Macnica
- ARIES Embedded - MCV System on Module
- Mpression Borax SOM Module and Development Kit by Macnica
- Enterpoint Mulldonoch 3
- Networked Pro-Audio FPGA SoC Development Kit by Coveloz
- NOVPEK™CVLite
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- NovTech IoT Octopus™
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- Enterpoint Raggedstone 4
- Solectrix SMARC compliant System-on-Module
- Terasic DE1-SoC Development and Education Board
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Recent Changes
-
Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series ~
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Docker Yocto Build
Using Docker to Build Yocto Recipes
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Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices -
GSRD for Agilex 7 I-Series Transceiver-SoC DevKit (4x F-Tile)
Golden System Reference Design for DK SI AGI027FB and DK SI AGI027FA -
Building Bootloader for Cyclone V and Arria 10
Information abut latest bootloaders for Cortex A9 based SoC FPGA devices
What is CvP? Why CvP?
What is CvP? Why CvP?
- Reduces system costs by reducing the size of the flash device to store the periphery configuration data.
- Improves security for the proprietary core bitstream. Configuration via Protocol ensures the PCIe host can exclusively access the FPGA core image.
- Enables dynamic core updates without requiring a system power down. Configuration via Protocol allows the FPGA fabric to be updated through the PCIe link without a host reboot or FPGA full chip reinitialization.
- Provides a simpler software model for configuration. A smart host can use the PCIe protocol and the application topology to initialize and update the FPGA fabric.
- Facilitates hardware acceleration.
- Reduces system size. You can use a single PCIe link to configure multiple FPGAs.
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