This tutorial is an introduction to the features of DS™-5 Debugger. The board has an Altera Cyclone V SoC, which has an FPGA as well as a dual core Cortex®-A9 processor. The tutorial demonstrates DS-5 features including bare metal debug, Linux kernel debug, trace and operating system awareness. In addition it teaches how to setup an FPGA adaptive debugging to control registers on the FPGA logic as well as cross triggering between the debugger and the Quartus SignalTap® II logic analyzer. The final section of the tutorial demonstrates the use of ARM Streamline for performance analyses and source code optimization.

Click on the DS-5 SoCKit Workshop.pdf link below to get started.

DS-5 SoCkit Workshop

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