Overview

System Console is an FPGA system debugging tool that is part of the Quartus II package.

This page demonstrates how to use the System Console to control the development board peripherals:

• Turn LEDs on and off
• Read pushbutton values
• Send characters to console through JTAG UART connection
• Read and write to the on-chip memory

Note that all the interaction happens between FPGA and System Console running on host PC. There is no software running on HPS.

Note that the examples on this page assume the Cyclone V GHRD is used. The Arria V usage is similar, the only change is that the file names are different.

Reference Material

For more information about GHRD see GHRD Overview.

For more information about System Console, refer to

• Analyzing and Debugging Designs with the System Console.
• System Console Whitepaper

Prerequisites

1. Unzip the GHRD archive cv_soc_devkit_ghrd.tar.gz to the home folder and use the instructions from Compiling the Hardware Design to compile the FPGA design.

2. Program the FPGA using Quartus II Programmer as described in FPGA Programming with Quartus II Programmer.

3. Reduce the JTAG speed to 16MHz to avoid instability issue on some board versions:

$ ~/altera/13.1/nios2eds/nios2_command_shell.sh
$ jtagconfig --setparam 1 JtagClock 16M 

Start System Console

1. Start Quartus II

~/altera/13.1/quartus/bin/quartus

2. In Quartus II, go to File → Open Project and select the file ~/cv_soc_devkit_ghrd/soc_system.qpf

3. In Quartus II, start the Qsys window by going to Tools → Qsys

4. When Qsys opens, it will ask for a .qsys file. Browse to*~/cv_soc_devkit_ghrd/soc_system.qsys* and click Open

5. In Qsys, go to Tools → System Console

6. Run the pwd command in system console to make sure the current folder is ~/cv_soc_devkit_ghrd/. If it is not, then execute cd command to change the current folder accordingly.

7. Run the GHRD script by typing source ghrd_sc_script.tcl

Controlling LEDs

The Development Kit has 4 LEDs that are connected to the FPGA. They are D5..D8 marked as FPGA LED 3..0. The LEDs are turned ON by default.

1. Use the following command to turn all LEDs off:

led_off

2. Turn on LED D5 by typing the following command:

led_on 0x7

3. Turn on LED D6 by typing the following command:

led_on 0xb

4. Turn on LED D7 by typing the following command:

led_on 0xd

5. Turn on LED D8 by typing the following command:

led_on 0xe

6. Turn all LED on by typing the following command

led_on 0x0

Reading Push Button State

The Development Kit has two push buttons that are connected to the FPGA. The are marked as FPGA button 0 and 1, also as S6 and S5.

1. Type the following command to clear the parallel I/O (PIO) data register:

button_data_read_clear

2. Type the following command to enable interrupts from push button S5:

button_intr_enable 0x1

3. Type the following command to start the interrupt monitoring in System Console:

irq_monitor_on

System Console will read the push button interrupt status every five seconds and display it on the console. It will initially show the button as not pressed.

4. Press button S5 on the development board. The irq monitor will indicate that the button is pressed until a button_data_read_clear will be run to clear the status.

5. Type the following command to turn off interrupt monitoring:

irq_monitor_off

Sending Characters Using JTAG UART

The GHRD contains a JTAG UART sof IP core, that can be used to transfer data between FPGA and the host PC. On the host PC, the data is handled by the nios2-terminal application.

1. Start the nios2-terminalapplication from a NIOS II command shell:

$ ~/altera/13.1/nios2eds/nios2_command_shell.sh
$ nios2-terminal

2. In System Console, type the following commands to send characters to the host PC:

juart_data_write 0x48
juart_data_write 0x49

3. The NIOS Console will display the two characters that were sent, spelling the word "HI":

Exercising Onchip RAM

The GHRD contains an FPGA Onchip memory soft IP core. The System Console TCL script includes a simple memory test routine that writes some values to random memory locations and reads them back to verify they are correct.

In order to run the memory test for 4 locations, type the following command in the System Console:

mem_rand_test 4