Release Notes

GSRD

• CV SoCFPGA GSRD, AV SoCFPGA GSRD and A10 SoCFPGA GSRD have been updated to use ACDS 18.0 and SoC EDS 18.0
• Arria 10 GSRD now supports Display Port

This Linux BSP release supports the SoC Development Kit, and provides the following:

• Linux kernel v4.9.78 LTSi
• Drivers: I2C, LCD, EEPROM, RTC, Ethernet, USB (Host), Watchdog, SD/MMC, QSPI, DMA, FPGA Manager, and FPGA Bridges

  Boards	U-Boot version	Binary location
  Stratix10 Devkit Rev A1	U-Boot v2017.09	Binary can acquired HERE
  Arria 10 Devkit Rev C	U-Boot v2014.10	Binaries are coupled in GHRD
  Cyclone V DevKit Rev E, Arria V DevKit Rev C	U-Boot v2013.01.01	Binary can acquired HERE

Preloader & U-Boot

It is highly recommended preloader and u-boot are built from the same commit.

Note: If SDRAM ECC is enabled in the Qsys design, please ensure that SDRAM ECC bit initialization is enabled in Preloader Generator

Release Contents

For 18.0 users are advised to follow the links for creating the SD image for:

Arria10:

Compile Linux Kernel and Root File System

Creating and updating SD Card Image with binaries for Arria 10

CycloneV and ArriaV:

Compile Linux Kernel and Root File System

Creating and updating SD Card Image with binaries for Arria V and Cyclone V

Stratix10:

Compile Linux Kernel and Root File System

Creating and updating SD Card Image with binaries for Stratix 10

Pre-Compiled jic and sof files for Stratix10

Silicon Revision	FPGA HW binaries	Remarks
Rev B	ghrd_1sx280lu2f50e2vgs2_hps.jic	Only for mt25qu02g flash
Rev B	ghrd_1sx280lu2f50e2vgs2_hps.sof	-
Rev C	ghrd_1sx280lu2f50e2vgs3_hps.jic	-
Rev C	ghrd_1sx280lu2f50e2vgs3_hps.sof	-

The Tools to create the SD Image can be downloaded from the link below:

tools

make_sdimage.py

SD Card Python Script

Before downloading the following hardware designs please read the agreement in the link https://www.altera.com/downloads/software/license/lic-prog_lic.html

Stratix10	s10_soc_devkit_ghrd.tar.gz	GHRD design
Arria10	a10_soc_devkit_ghrd.tar.gz	GHRD design
Arria10	a10_soc_devkit_ghrd_nand.tar.gz	NAND design
Arria10	a10_soc_devkit_ghrd_qspi.tar.gz	QSPI design
Arria10	a10_soc_devkit_pcie_gen2x8.tar.gz	PCIE2x8 design
Arria10	a10_soc_devkit_pr.tar.gz	PR design
Arria10	a10_soc_devkit_sgmii.tar.gz	SGMII design
Arria10	a10_soc_devkit_tse.tar.gz	TSE design
Cyclone5	cv_soc_devkit_ghrd.tar.gz	GHRD design
Cyclone5	cv_soc_devkit_pcie.tar.gz	PCIE design
Arria5	av_soc_devkit_ghrd.tar.gz	GHRD design
Arria5	av_soc_devkit_PCIE.tar.gz	PCIE design

The following documents are also part of the release:

Document	Description
GSRD v18.0 - Stratix 10 User Manual	User Manual
GSRD v18.0 - Arria 10 User Manual	User Manual
GSRD v18.0 - Cyclone and Arria V User Manual	^

U-boot, Linux kernel and Yocto source packages are also provided through the git trees at https://github.com/altera-opensource, as shown in the table below.

Component	Git address	Branch	Tag
Linux	linux-socfpga.git	socfpga-4.9.78-ltsi	ACDS18.0_REL_GSRD_PR
U-Boot (S10)	u-boot-socfpga.git	socfpga_v2017.09	ACDS18.0_REL_S10_GSRD_PR
SPL/U-Boot (CV/AV)	u-boot-socfpga.git	socfpga_v2013.01.01	ACDS18.0_REL_GSRD_PR
Ref Designs	linux-refdesigns.git	master	ACDS18.0_REL_GSRD_PR

Note: sometimes it can be useful to try the latest from the branch, instead of the tag, as bug fixes and features are released on github periodically. However, when doing so, care must be exercised as that specific combination of versions will not be part of a fully tested GSRD. You may monitor the git commit messages on the branch, to see the history.