Compile Hardware Design 16.1 Arrow SoCKit Edition

Overview

This page demonstrates how to compile the FPGA Hardware design that is delivered as part of the GSRD release.

The compilation will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.sopcinfo	SOPC Info File - containing a description of the hardware to be used by Device Tree Generator
.svd	System View Description File - describes the hardware for the DS-5 debugger
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

Prerequisites

The following items are required:

• Host PC running Linux (CentOS 6.3 or newer or Ubuntu 12.04LTS or newer preferred) or Windows
• Altera Quartus™ II v16.1 - available from http://www.altera.com/products/software/sfw-index.jsp
• GHRD Archive from github

Procedure

1. Open a Windows or Linux shell and cd to the home folder.

2. Clone the github archive

$ git clone https://github.com/arrow-socfpga/arrow-sockit-ghrd
$ cd arrow-sockit-ghrd

3. Checkout a branch (sockit-ghrd-16.1 or sockit-ghrd-1080p-16.1)

$ git checkout sockit-ghrd-16.1

4. Start Quartus tool by double clicking the icon on the desktop, or by running it from the command line:

$ ~/altera/16.1/quartus/bin/quartus --64bit 

5. In Quartus, go to File → Open Project ..., browse to the file sockit_ghrd/soc_system.qpf and click Open.

6. Quartus will load the project.

Generate System in Qsys

7. In Quartus, go to Tools → Qsys to start the Qsys tool

8. Qsys tool will start and ask you to open a Qsys file. Select sockit_ghrd/soc_system.qsys and click Open.

9. Qsys will load the file

10. In Qsys, select Generate -≫ Generate this will open the Generate dialogue box.

11. In the Generate dialogue box, click the Generate button.

12. A message will be displayed when the generation is complete (may take a few minutes depending on host machine speed)

13. Click Close button in the Generation window to close it.

14. In Qsys, go to File → Exit to close Qsys.

Compile the Design in Quartus

Running Analysis & Synthesis

15. In Quartus, in the Tasks panel change the flow from RTL Simulation to Compilation.

16. In the Tasks panel, right click Analysis and Synthesis and select Start.

17. After a few minutes (depending on host machine speed) the Analysis & Synthesis will finish and a message will be displayed.

Running the Assembler

18. In the Tasks panel, select Assembler, right click it and select Start.

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19. After the assembly phase is completed, a notification message will be displayed.

Generated Files

This section presents the name and location of the files generated as a result of compiling the hardware design.

File	Description
sockit_ghrd/output_files/soc_system.sof	SRAM Object File - for programming FPGA
sockit_ghrd/soc_system.sopcinfo	SOPC Info File - Used by Device Tree Generator
sockit_ghrd/soc_system/synthesis/soc_system_hps_0_hps.svd	System View File - Used by ARM DS-5 AE
sockit_ghrd/hps_isw_handoff	Handoff folder - Used by Preloader Generator

Converting .sof to .rbf

The SOF (SRAM Object File) file can use used to program the FPGA from the Quartus Programmer tool.

However, for the purpose of programming the FPGA from software, the SOF file needs to be converted to a RBF (Raw Binary File) format.

Use the command line tools from the Quartus Programmer (installed by default with the SoC EDS or installed standalone) or from Quartus to create the rbf file.

 $ ~/altera/16.1/quartus/bin/quartus_cpf -c \
  -o bitstream_compression=on \
  sockit_ghrd/output_files/soc_system.sof  \
  sockit_ghrd/output_files/soc_system.rbf