RocketBoards- Home
- Documentation
- Community
- Projects
- Boards
- Agilex 5 SoC
- Agilex 7 SoC
- Arria 10 SoC
- Nallatech 385A - Arria 10 FPGA Network Accelerator Card
- Nallatech 385A-SoC Accelerator Card with Arria 10 FPGA
- ALARIC Instant DevKit ARRIA 10 SoC FMC IDK by REFLEX CES
- Altera Arria 10 SoC Virtual Platform
- Altera Arria 10 SoC Board
- Nallatech 510T compute acceleration card with Intel Arria 10 FPGA
- REFLEX CES Achilles Arria 10 SoC SOM
- Terasic Arria10 SoC Board : HAN Pilot Platform
- Arria V SoC
- Cyclone V SoC
- Altera Cyclone V SoC Board
- Arrow SoCKit User Manual - July 2017 Edition
- Arrow SoCKit User Manual - November 2019 Edition
- Arrow SoCKit Evaluation Board
- Atlas-SoC Development Platform
- Critical Link MitySOM-5CSx Development Kit
- Cyclone V Ethernet driver problems
- DE10-Nano Development Board
- Terasic DE10-Standard Development Kit
- Devboards DBM-SoC1 module
- Devboards DBM-SoC2 module
- EBV SoCrates Evaluation Board
- Enclustra Mercury SA1 SoC Module
- Enterpoint Drigmorn 5
- Enterpoint Larg 2
- Altera Cyclone V SoC Development Platform
- Mpression Helio SoC Evaluation Kit by Macnica
- Mpression Sodia Evaluation Board by Macnica
- ARIES Embedded - MCV System on Module
- Mpression Borax SOM Module and Development Kit by Macnica
- Enterpoint Mulldonoch 3
- Networked Pro-Audio FPGA SoC Development Kit by Coveloz
- NOVPEK™CVLite
- NOVSOM®CV
- NOVSOM®CVLite
- NovTech IoT Octopus™
- NovTech NetLeap™
- Enterpoint Raggedstone 4
- Solectrix SMARC compliant System-on-Module
- Terasic DE1-SoC Development and Education Board
- Stratix 10 SoC
- Find a Board
- News
Generating the Device Tree How to generate the device tree source and how to compile it to a device tree blob file that Linux needs
Configuration
Board(s):
Altera Cyclone V SoC BoardAltera Arria V SoC BoardTools Version(s):
17.0std, 17.1std, 18.0std, 18.1std, 17.0std, 17.1std, 18.0std, 18.1stdTags:
device tree, dtb- Select a different Task
Similar topics
-
HOWTO Create a Devicetree for Agilex SoC
Advice on how to create a devicetree for SoC FPGA linux environments.
-
HOWTO Create a Devicetree for Arria 10 SoC
Advice on how to create a devicetree for SoC FPGA linux environments.
-
HOWTO Create a Devicetree for Cyclone V SoC
Advice on how to create a devicetree for SoC FPGA linux environments.
-
HOWTO Create a Devicetree for Stratix 10 SoC
Advice on how to create a devicetree for SoC FPGA linux environments.
-
HOWTO Create a Device Tree
Advice on how to create a device tree for SoC FPGA linux environments.
Recent Changes
-
Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series ~
-
Docker Yocto Build
Using Docker to Build Yocto Recipes
-
Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices -
GSRD for Agilex 7 I-Series Transceiver-SoC DevKit (4x F-Tile)
Golden System Reference Design for DK SI AGI027FB and DK SI AGI027FA -
Building Bootloader for Cyclone V and Arria 10
Information abut latest bootloaders for Cortex A9 based SoC FPGA devices
Overview
Reference Information
For detailed information about the Device Tree Generator see Device Tree Generator User Guide.Prerequisites
The following items are required:- Host PC running Linux (CentOS 6.8 or Ubuntu 14.04LTS are preferred)
- Intel SoC EDS Software - from https://www.altera.com/download/software/soc-eds
- GHRD Archive: https://releases.rocketboards.org/
Procedure
Cyclone V
1. Compile the GHRD as described in Compiling the Hardware Design to obtain the .sopcinfo file. 2. Start an Embedded Command Shell and go to GHRD folder (assumed here to be saved in the home folder):$ ~/intelFPGA/3. Run the Device Tree Generator/embedded/embedded_command_shell.sh $ cd ~/cv_soc_devkit_ghrd
$ sopc2dts --input soc_system.sopcinfo\This will generate the file ~/cv_soc_devkit_ghrd/socfpga.dtb required by Linux to boot.
--output socfpga.dtb\
--type dtb\
--board soc_system_board_info.xml\
--board hps_common_board_info.xml\
--bridge-removal all\
--clocks
Arria V
1. Compile the GHRD as described in Compiling the Hardware Design to obtain the .sopcinfo file. 2. Start an Embedded Command Shell and go to GHRD folder (assumed here to be saved in the home folder):$ ~/intelFPGA/3. Run the Device Tree Generator/embedded/embedded_command_shell.sh $ cd ~/av_soc_devkit_ghrd
$ sopc2dts --input ghrd_5astfd5k3.sopcinfo\This will generate the file ~/av_soc_devkit_ghrd/socfpga.dtb required by Linux to boot.
--output socfpga.dtb\
--type dtb\
--board ghrd_5astfd5k3_board_info.xml\
--board hps_common_board_info.xml\
--bridge-removal all\
--clocks
© 1999-2024 RocketBoards.org by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
This website is using cookies. More info.
That's Fine