THIS IS A DRAFT PAGE FOR 15.1.1 WHICH IS YET TO BE RELEASED

Overview

The Arria 10 Golden Hardware Reference Design is an important part of the Arria 10 Golden System Reference Design (GSRD) User Manuals and consists of the following components:

• ARM Cortex™-A9 MPCore HPS
• Two user push-button inputs
• Four user DIP switch inputs
• Four user I/O for LED outputs
• 64KB of on-chip memory
• JTAG to Avalon master bridges
• Interrupt capturer for use with System Console
• System ID

The GHRD has a minimal set of peripherals in the FPGA fabric, because the HPS provides a substantial selection of peripherals.

HPS-to-FPGA and FPGA-to-HPS interfaces are configured to a 64-bit data width.

The Arria10 GHRD allows hardware designers to access each peripheral in the FPGA portion of the SoC with System Console, through the JTAG master module. This signal-level access is independent of the driver readiness of each peripheral.

Changes to Arria 10 in 15.1.1 onwards

The Arria 10 GHRD from the 15.1.1 release onwards allows up to 3 EMAC to be enabled. Two of the EMAC will use SGMII.

MPU Address Maps

This section presents the address maps as seen from the MPU (A9) side.

HPS-to-FPGA Address Map

The memory map of soft IP peripherals, as viewed by the microprocessor unit (MPU), starts at HPS-to-FPGAaddress offset 0xC000_0000. The following table lists the offset of each peripheral in the FPGA portion of the SoC.

Peripheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0	64K	On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.

Peripheral	Address Offset	Size (bytes)	Attribute
sysid_qsys	0x10000	8	Unique system ID
led_pio	0x10040	8	LED output display
dipsw_pio	0x10080	8	Push button input
button_pio	0x100c0	8	DIP switch input
jtag_uart	0x20000	8	JTAG UART console

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGAfabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral	Address Offset	Size (bytes)	Attribute
sysid_qsys	0x0001_0000	8	Unique system ID
led_pio	0x0001_0040	8	4 LED outputs
dipsw_pio	0x0001_0080	8	4 DIP switch inputs
button_pio	0x0001_00c0	8	2 push button inputs
jtag_uart	0x0002_0000	8	JTAG UART console
onchip_memory2_0	0x0000_0000	64K	On-chip RAM

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Peripheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0[0]	4 DIP switch inputs
button_pio	f2h_irq0[1]	2 push button inputs
jtag_uart	f2h_irq0[2]	JTAG UART

The interrupt sources are also connected to an interrupt capturer module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.