RocketBoards- Home
- Documentation
- Community
- Projects
- Boards
- Agilex 5 SoC
- Agilex 7 SoC
- Arria 10 SoC
- Nallatech 385A - Arria 10 FPGA Network Accelerator Card
- Nallatech 385A-SoC Accelerator Card with Arria 10 FPGA
- ALARIC Instant DevKit ARRIA 10 SoC FMC IDK by REFLEX CES
- Altera Arria 10 SoC Virtual Platform
- Altera Arria 10 SoC Board
- Nallatech 510T compute acceleration card with Intel Arria 10 FPGA
- REFLEX CES Achilles Arria 10 SoC SOM
- Terasic Arria10 SoC Board : HAN Pilot Platform
- Arria V SoC
- Cyclone V SoC
- Altera Cyclone V SoC Board
- Arrow SoCKit User Manual - July 2017 Edition
- Arrow SoCKit User Manual - November 2019 Edition
- Arrow SoCKit Evaluation Board
- Atlas-SoC Development Platform
- Critical Link MitySOM-5CSx Development Kit
- Cyclone V Ethernet driver problems
- DE10-Nano Development Board
- Terasic DE10-Standard Development Kit
- Devboards DBM-SoC1 module
- Devboards DBM-SoC2 module
- EBV SoCrates Evaluation Board
- Enclustra Mercury SA1 SoC Module
- Enterpoint Drigmorn 5
- Enterpoint Larg 2
- Altera Cyclone V SoC Development Platform
- Mpression Helio SoC Evaluation Kit by Macnica
- Mpression Sodia Evaluation Board by Macnica
- ARIES Embedded - MCV System on Module
- Mpression Borax SOM Module and Development Kit by Macnica
- Enterpoint Mulldonoch 3
- Networked Pro-Audio FPGA SoC Development Kit by Coveloz
- NOVPEK™CVLite
- NOVSOM®CV
- NOVSOM®CVLite
- NovTech IoT Octopus™
- NovTech NetLeap™
- Enterpoint Raggedstone 4
- Solectrix SMARC compliant System-on-Module
- Terasic DE1-SoC Development and Education Board
- Stratix 10 SoC
- Find a Board
- News
Documentation
Similar topics
- Mpression Helio SoC Evaluation Kit by Macnica
-
Mpression Borax SOM Module and Development Kit by Macnica
The Mpression Borax SOM is a system on module card integrating an Altera® Cyclone® V SoC FPGA and necessary memory, power and external interfaces on a very small size card and uses an Altera Cyclone V SoC FPGA tightly integrates two ARM Cortex A9 cores and FPGA fabric
- Rocketboards Contributor Wall Of Fame
-
SoC Device Resources
- Enterpoint Mulldonoch 3
Recent Changes
-
Macnica Sulfur ~ Development Kit for Agilex™ 5 FPGA E-Series ~
-
Docker Yocto Build
Using Docker to Build Yocto Recipes
-
Building Bootloader for Agilex 5
Building latest bootloaders for Agilex 5 SoC Devices -
GSRD for Agilex 7 I-Series Transceiver-SoC DevKit (4x F-Tile)
Golden System Reference Design for DK SI AGI027FB and DK SI AGI027FA -
Building Bootloader for Cyclone V and Arria 10
Information abut latest bootloaders for Cortex A9 based SoC FPGA devices
Table of Contents
Introduction
The Sodia evaluation board is enabling to evaluate more widely applications of ARM®Cortex®-A9 by higher extensibility with two extension connectors(HSMC). This evaluation board enables to develop the embedded system designs quickly which can bridge to the real applications. And the Sodia is a higher model of Macnica Helio SoC Evaluation Kit (Cyclone®V SoC starter kit) and is most suitable for users who hope the expansion from Helio. Around HPS function same as Helio, and software is compatible.
Board photos
Top view
Bottom view
Board block diagram
Board Features
The Macnica Sodia Cyclone V SoC evaluation board features the following:- Featured device
- FPGA configuration sources
- Quad-Serial Configuration flash -- EPCQ 256Mbit
- Hard processor system (HPS)
- USB-BlasterTM or USB-BlasterTM II Download Cable
- FPGA memory
- 256MB DDR3 SDRAM (32 bit)
- FPGA I/O interfaces
- x2 High Speed Mezzanine Card (HSMC) connectors
- Port A: x4 transceivers, x17 TX LVDS, x17 RX LVDS
- Port B: x2 transceivers, x17 TX LVDS, x17 RX LVDS
- x1 Digital Visual Interface(DVI) output interface
- x1 Audio interface (Line-in/out, Mic-in)
- x2 push buttons
- x2 switches
- x4 LEDs
- x2 High Speed Mezzanine Card (HSMC) connectors
- HPS boot sources
- 64 MB QSPI Flash
- Removable SD Card flash
- FPGA
- HPS memory
- 1 GB DDR3 SDRAM (32 bit) with error correction code (ECC)
- 64 MB QSPI flash
- 4kB EEPROM
- HPS I/O interfaces
- x1 SD Card socket
- x1 USB 2.0 Host
- x1 10/100/1000 Gigabit Ethernet
- x1 UART (UART to USB bridge)
- x1 real-time clock (with battery backup)
- x4 push buttons
- x4 switches
- x4 LEDs
- Clocking
- 100 / 148.5 MHz LVDS oscillator for FPGA reference clock input
- 125 MHz LVDS programmable oscillator for FPGA reference clock input
- 25 MHz single-ended oscillator for HPS clock input
- 27 / 50 / 100 MHz single-ended oscillator for FPGA clock input
- SMA input for HPS clock
- SMA input for FPGA clock
- Power
- DC input 12 V Adaptor
- Ambient Temperature Range (Operating)
- 5 ~ +35 degrees
- Storage Temperature Range（Non-operating）
- 5 ~ +35 degrees
- Humidity Range
- 85% R.H. Maximum. No condensation permitted.
- Storage area is to be free of dust, corrosive gases and dew formation.
- Mechanical size
- 200mm x 150mm
Documentation
| Category | Item | Rev. | Download | Note |
|---|---|---|---|---|
| Documentation | Getting Started | 1.1 | EN: English JP: Japanese |
|
| ^ | Reference Manual | 1.0 | EN: English JP: Japanese |
|
| Board References | Schematic | A | sodia_board_SCH_revA.pdf | |
| ^ | ^ | B | sodia_board_SCH_revB.pdf | part# changed(QSPI) |
| ^ | ^ | C | sodia_board_SCH_revC.pdf | part# changed(DDR3) |
| ^ | Bill of Materials | A | sodia_board_BOM_revA.xlsx | |
| ^ | ^ | B | sodia_board_BOM_revB.xlsx | part# changed(QSPI) |
| ^ | ^ | C | sodia_board_BOM_revC_.xlsx |
part# changed(DDR3) |
| ^ | PWB data | A | sodia_board_PWB_revA.pdf | |
| ^ | ^ | A | sodia_board_PWB_revA.brd | Allegro data |
Basic Reference Designs
| Item | Rev. | Download | Note |
|---|---|---|---|
| HW Reference Design | v2.0 | sodia_ghrd_v20.1.zip |
|
| ^ | v1.4 | sodia_ghrd_v18.1.0.zip |
|
| ^ | v1.2 | sodia_ghrd_v17.1.0.zip |
|
| ^ | v1.1 | sodia_ghrd_v16.1.0.zip |
|
| ^ | v1.0 | sodia_ghrd_v15.1.2.zip |
|
| Linux SD Card Image | v2.0b | sodia_gsrd_sdimage_5.4.104-lts_b.tgz | Linux Kernel : v5.4.104-lts Rootfs : Yocto Poky 3.1.7 (dunfell) OSS sources and build infos are here here. |
| ^ | v1.4b | sodia_gsrd_sdimage_4.14.130-ltsi_b.tgz | Linux Kernel : v4.14.130-ltsi Rootfs : Angstrom 2019.06 OSS sources and build infos are here. |
| ^ | v1.4a | sodia_gsrd_sdimage_4.14.73-ltsi_a.tgz | Linux Kernel : v4.14.73-ltsi Rootfs : Angstrom 2018.06 OSS sources and build infos are here. |
Other Reference Designs
| Item | Rev. | Download | Note |
|---|---|---|---|
| HW Reference Design with DDR3 FPGA Side | v1.4 | sodia_ghrd_with_fpga_ddr_v18.1.0.zip |
|
| HW Reference Design with DDR3 FPGA Side | v1.1 | sodia_ghrd_with_fpga_ddr_v17.1.0.zip |
|
| HW Reference Design with DDR3 FPGA Side | v1.0 | sodia_ghrd_with_fpga_ddr_v16.1.0.zip |
|
| HW Reference Design with DVI output interface | ‐ | Uploaded to the another page. [ Click Here ] |
‐ |
| HW Design and SD Card Image for audio input/output | - | Uploaded to the another page. [ Click Here ] |
‐ |
Demo
- Low Latency Warping Demo
- OpenCL Mandelbrot Demo
- Sodia LVDS Panel & SDI Camera Demo
- Sodia Ubuntu Nano Image
- Sodia Ubuntu Desktop Image
- Development OpenCL on Sodia Board
- Sodia Debian Base Desktop Image
- Sodia QSPI Boot
日本語リソース
- SoC 日本語ポータル
- Sodia ボードを使用した OpenCL 開発
- EPCQ コントローラ向けデバイスドライバの実装
- Sodia ボード製品ページ(マクニカオンラインサービス)
- Preloader Generator の使用方法 (マクニカオンラインサービス)
- Linux / Android 高速起動ソリューション Ubiquitous QuickBoot のご紹介（Mpression Sodia ボード向け）(マクニカオンラインサービス)
Related Links
© 1999-2024 RocketBoards.org by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
This website is using cookies. More info.
That's Fine