Nallatech 510T compute acceleration card with Intel Arria 10 FPGA
The Nallatech 510T Compute Acceleration Card is an FPGA co-processor that is designed to deliver ultimate performance per watt for compute-intensive datacenter applications.

28 Jun 2017 - 21:24 | Version 6 | | , , , , ,
Nallatech 510T - with two Intel Arria 10 FPGAs

510T – with Arria 10 / Datacenter Co-Processor FPGA Compute Acceleration Card

The Nallatech 510T Compute Acceleration Card is an FPGA co-processor that is designed to deliver ultimate performance per watt for compute-intensive datacenter applications.

The 510T Compute Acceleration Card is a GPU-sized 16-lane PCIe Gen 3 card featuring two of Altera’s new floating-point enabled Arria 10 FPGAs delivering up to sixteen times the performance of the previous generation. Applications can achieve a total sustained performance of up to 3 TFlops.

510T Compute Acceleration Card deliverables include an optimized Board Support Package compatible with the Altera Software Development Kit (SDK) for OpenCL. This allows the card to be programmed at a high level of abstraction by customers unfamiliar with hardware-based tool flows historically required for FPGAs.

The 510T Compute Acceleration Card is available with an unprecedented 290GByte/sec of peak external memory bandwidth configured as eight independent banks of DDR4 plus an ultra-fast Hybrid Memory Cube (HMC). This combination, plus the FPGA’s on-chip memory bandwidth of 14.4TBytes/sec, permits dramatic new levels of performance per watt for memory-bound applications.

510T-Diagram-500x2642x.jpg

ARM-based SoC delivers optimal performance, power efficiency and low cost for real-time applications

opencl logo-52x502x.png Nallatech 510T - FPGA PCIe Acclerator Card - GPU Size Form Factor

  • GPU Form Factor Card with (2) Arria 10 10A1150GX FPGAs
  • Dual Slot Standard Configuration
  • Single Slot width possible, if user design fits within ~100W power footprint
  • PCIe Gen3 x 16 Host Interface
  • 290 GBytes/s Peak Aggregate Memory Bandwidth
  • 85GB/s Peak DDR4 Memory Bandwidth per FPGA (4 Banks per FPGA)
  • 30GB/s Write + 30GB/s Read Peak HMC Bandwidth per FPGA

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