Note that the contents of this page only refers to 13.1 version of tools. For newer versions of the tools, the sane effect can be achieved directly from Qsys.

Overview

The following figure presents an overview of the Preloader Generation process.

The Preloader Generator creates the source code for configuring the HPS clocks, in the file pll_config.h using the following:

• A fixed configuration for Main and Peripheral PLLs
• Parameters generated by Quartus in the handoff file emif.xml for SDRAM PLL.

If the user needs to change SDRAM clocking parameters, he or she can do it in Qsys, following the regular flow. However, if the user needs to change other clocking parameters, he or she will need to manually update the pll_config.h file that is created by the Preloader Generator, then recompile the Preloader.

This page:

• Presents an overview of the HPS Clocking scheme,
• Lists all Preloader clocking parameters, as defined in pll_config.h,
• Lists all the clocks in the system, calculated using the Preloader clocking parameters,
• Enables the user to change clocking parameters and generate the pll_config.h file automatically.

Warning: The calculator provided by this page does not fully validate the frequencies. Please use the Datasheet and the Clock Manager documentation to make sure the parameters fit in the correct range for the specific device you are using.

Device	Document	Link
Arria V	Clock Manager	http://www.altera.com/literature/hb/arria-v/av_54002.pdf
^	Datasheet	http://www.altera.com/literature/hb/arria-v/av_51002.pdf
Cyclone	Clock Manager	http://www.altera.com/literature/hb/cyclone-v/cv_54002.pdf
^	Datasheet	http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf

HPS Clock Tree

This section presents an overview of the HPS clocking tree.

For detailed information on SoC Clocking please refer to:

• For Cyclone V
  • Cyclone V SoC Clock Manager
  • Cyclone V SoC Memory Map and Register Definitions - section "clkmgr"
• For Arria V
  • Arria V SoC Clock Manager
  • Arria V SoC Memory Map and Register Definitions - section "clkmgr"

Clock Tree Overview

This following picture presents a top level view of the HPS clock tree:

Generic PLL Operation

The following picture presents a summary on how the HPS PLLs work:

Main PLL Clocks

This section presents a summary of the clocks derived from Main PLL.

Peripheral PLL Clocks

This section presents a summary of the clocks derived from Peripheral PLL.

Flash Memory Clocks

This section presents a summary of the Flash memory clocks.

SDRAM PLL Clocks

This section presents a summary of the clocks derived from SDRAM PLL.

HPS Reference Input Clocks

This section lists the possible input reference clocks. The values are populated with the default Preloader values, as created by the Preloader Generator, but they can also be edited to match a custom board design.

Input Clock	Value	Description
EOSC1		External OSC1 reference clock
EOSC2		External OSC2 reference clock
f2h_sdram_ref_clk		FPGA 2 HPS reference clock
f2h_periph_ref_clk		FPGA 2 HPS reference peripheral clock

Preloader Parameters

Main PLL Parameters

This section presents the Main PLL parameters, as defined in he file pll_config.h. The fields are populated with the default Preloader values, but can also be edited.

Parameter	Value	Min	Max	Description
CONFIG_HPS_MAINPLLGRP_VCO_DENOM		0	63	PLL denominator
CONFIG_HPS_MAINPLLGRP_VCO_NUMER		0	4,095	PLL numerator
CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT		0	511	C0 divider
CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT		0	511	C1 divider
CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT		0	511	C2 divider
CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT		0	511	C3 divider
CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT		0	511	C4 divider
CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT		0	511	C5 divider
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK		0	1	l3_mp_clk divider
CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK		0	1	l3_sp_clk divider
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK		0	4	l4_mp_clk divider
CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK		0	4	l4_sp_clk divider
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK		0	2	dbg_at_clk divider
CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK		1	2	dbg_clk divider
CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK		0	4	dbg_trace_clk divider
CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP		0	1	l4_mp_clk source: 0 - main_base_clk, 1 - periph_base_clk.
CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP		0	1	l4_sp_clk source: 0 - main_base_clk, 1 - periph_base_clk.

Peripheral PLL Parameters

This section presents the Peripheral PLL parameters, as defined in he file pll_config.h. The fields are populated with the default Preloader values, but can also be edited.

Parameter	Value	Min	Max	Description
CONFIG_HPS_PERPLLGRP_VCO_DENOM		0	63	PLL denominator
CONFIG_HPS_PERPLLGRP_VCO_NUMER		0	4,095	PLL numerator
CONFIG_HPS_PERPLLGRP_VCO_PSRC		0	2	PLL input clock: 0 - EOSC1, 1 - EOSC2, 2 - f2h_periph_ref_clk
CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT		0	511	C0 divider
CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT		0	511	C1 divider
CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT		0	511	C2 divider
CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT		0	511	C3 divider
CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT		0	511	C4 divider
CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT		0	511	C5 divider
CONFIG_HPS_PERPLLGRP_DIV_USBCLK		0	4	usb_mp_clk divider
CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK		0	4	spi_m_clk divider
CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK		0	4	can0_clk divider
CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK		0	4	can1_clk divider
CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK		0	16,777,215	gpio_db_clk divider
CONFIG_HPS_PERPLLGRP_SRC_SDMMC		0	2	sdmmc_clk source: 0 - f2h_periph_ref_clk, 1 - main_nand_sdmmc_base_clk, 2 - periph_nand_sdmmc_base_clk.
CONFIG_HPS_PERPLLGRP_SRC_NAND		0	2	nand_clk source: 0 - f2h_periph_ref_clk, 1 - main_nand_sdmmc_base_clk, 2 - periph_nand_sdmmc_base_clk.
CONFIG_HPS_PERPLLGRP_SRC_QSPI		0	2	qspi_clk source: 0 - f2h_periph_ref_clk, 1 - main_qspi_base_clk, 2 - periph_qspi_base_clk.

SDRAM PLL Parameters

This section presents the SDRAM PLL parameters, as defined in he file pll_config.h. The fields are populated with the default Preloader values, but can also be edited.

Parameter	Value	Min	Max	Description
CONFIG_HPS_SDRPLLGRP_VCO_DENOM		0	63	PLL denominator
CONFIG_HPS_SDRPLLGRP_VCO_NUMER		0	4,095	PLL numerator
CONFIG_HPS_SDRPLLGRP_VCO_SSRC		0	2	PLL input clock: 0 - EOSC1, 1 - EOSC2, 2 - f2h_sdram_ref_clk.
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT		0	511	C0 divider
CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE		0	4,095	C0 phase
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT		0	511	C1 divider
CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE		0	4,095	C1 phase
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT		0	511	C2 divider
CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE		0	4,095	C2 phase
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT		0	511	C5 divider
CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE		0	4,095	C5 phase

The SDRAM PLL parameters are not fixed by the Preloader Generator, instead they are copied from the handoff file named emif.xml. Do not change the parameters directly in pll_config.h, but instead follow this procedure:

1. Change the SDRAM parameters in Qsys
2. Recompile the design in Quartus to update the handoff files
3. Generate the Preloader
4. Compile the Preloader

Note that the manual edits from pll_config.hwill be lost once the Preloader is generated again.

Computed Clocks

This section presents the output clock values, computed based on the reference input clocks and the Preloader Parameters. The values are populated with the default Preloader values, and can be recomputed by pressing the corresponding button.

Computed Main PLL Clocks

Clock	Value
VCO: main_pll_vco_clk
C0: mpu_base_clk
C1: main_base_clk
C2: dbg_base_clk
C3: main_qspi_base_clk
C4: main_nand_sdmmc_base_clk
C5: cfg_h2f_user0_base_clk
mpu_periph_clk
mpu_l2_ram_clk
mpu_clk
l4_main_clk
l3_main_clk
l3_mp_clk
l3_sp_clk
l4_mp_clk
l4_sp_clk
dbg_at_clk
dbg_clk
dbg_trace_clk
dbg_timer_clk
cfg_clk
h2f_user0_clock

Computed Peripheral PLL Clocks

Clock	Value
VCO: periph_pll_vco_clk
C0: emac0_base_clk
C1: emac1_base_clk
C2: periph_qspi_base_clk
C3: periph_nand_sdmmc_base_clk
C4: periph_base_clk
C5: h2f_user1_base_clk
emac0_clk
emac1_clk
usb_mp_clk
spi_m_clk
can0_clk
can1_clk
gpio_db_clk
h2f_user1_clock
sdmmc_clk
nand_x_clk
nand_clk
qspi_clk

Computed SDRAM PLL Clocks

Clock Name	Clock Frequency
VCO: sdramm_pll_vco_clk
C0: ddr_dqs_base_clk
C1: ddr_2x_dqs_base_clk
C2: ddr_dq_base_clk
C5: h2f_user2_base_clk
ddr_dqs_clk
ddr_2x_dqs_clk
ddr_dq_clk
h2f_user2_clock

Generated Source Code

This section presents the contents of the pll_config.hfile. The file is populated with the default Preloader values, but can be updated by pressing the button below.

#ifndef _PRELOADER_PLL_CONFIG_H_
#define _PRELOADER_PLL_CONFIG_H_

#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM             (0)
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER             (63)
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT            (0)
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT           (0)
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT          (0)
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT       (3)
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT  (3)
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT    (15)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK       (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK       (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK       (1)
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK       (1)
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK       (0)
#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK         (1)
#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK     (0)
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP            (1)
#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP            (1)

#define CONFIG_HPS_PERPLLGRP_VCO_DENOM              (1)
#define CONFIG_HPS_PERPLLGRP_VCO_NUMER              (79)
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC               (0)
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT           (3)
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT           (3)
#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT         (1)
#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT    (4)
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT         (4)
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT        (9)
#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK             (0)
#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK            (0)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK            (1)
#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK            (1)
#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK      (6249)
#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC              (2)
#define CONFIG_HPS_PERPLLGRP_SRC_NAND               (2)
#define CONFIG_HPS_PERPLLGRP_SRC_QSPI               (1)

#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM              (0)
#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER              (31)
#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC               (0)
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT          (1)
#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE        (0)
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT        (0)
#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE      (0)
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT           (1)
#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE         (4)
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT        (5)
#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE      (0)

#define CONFIG_HPS_CLK_OSC1_HZ                      (25000000)
#define CONFIG_HPS_CLK_MAINVCO_HZ                   (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ                    (1000000000)
#define CONFIG_HPS_CLK_SDRVCO_HZ                    (800000000)
#define CONFIG_HPS_CLK_EMAC0_HZ                     (250000000)
#define CONFIG_HPS_CLK_EMAC1_HZ                     (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ                    (200000000)
#define CONFIG_HPS_CLK_NAND_HZ                      (50000000)
#define CONFIG_HPS_CLK_SDMMC_HZ                     (200000000)
#define CONFIG_HPS_CLK_QSPI_HZ                      (400000000)
#define CONFIG_HPS_CLK_SPIM_HZ                      (200000000)
#define CONFIG_HPS_CLK_CAN0_HZ                      (100000000)
#define CONFIG_HPS_CLK_CAN1_HZ                      (100000000)
#define CONFIG_HPS_CLK_GPIODB_HZ                    (32000)
#define CONFIG_HPS_CLK_L4_MP_HZ                     (100000000)
#define CONFIG_HPS_CLK_L4_SP_HZ                     (100000000)

#endif

Partial Clock Validation

Warning: The calculator provided by this page does not fully validate the frequencies. Please use the Datasheet and the Clock Manager documentation to make sure the parameters fit in the correct range for the specific device you are using.

Device	Document	Link
Arria V	Clock Manager	http://www.altera.com/literature/hb/arria-v/av_54002.pdf
^	Datasheet	http://www.altera.com/literature/hb/arria-v/av_51002.pdf
Cyclone	Clock Manager	http://www.altera.com/literature/hb/cyclone-v/cv_54002.pdf
^	Datasheet	http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf

Press the button to perform a partial validation of the clocks. It will first recompute the clocks and generate the source code.