Enabling ECC for HPS SDRAM

Overview

This page presents the steps to enable Error Checking and Correction (ECC) on HPS SDRAM. Currently, the ECC controller supports auto correction for single bit errors, while double-bit errors and address mismatch will be flagged but not auto corrected.

This example show the steps to enable HPS EMIF width of either 72-bit (64 + 8 bit ECC) or 40-bit (32 + 8 bit ECC) for the Stratix 10 GSRD. ECC is also supported in 24-bit (16 + 8-bit ECC) memory width interfaces.

Prerequisites

The following items are required:

• Host PC running Linux (tested in Ubuntu 16.04LTS)
  • Note that for Stratix 10 project compilation, the recommended amount of physical RAM is between 80 - 128 GB
• Intel Quartus™ Prime Pro and GHRD Archive according to Release Tags.
• Intel SoC FPGA EDS Pro Edition

Opening and Editing Platform Designer File

1. The following steps assumes that you have downloaded a copy of the Stratix 10 GHRD. If you do not have a copy of the GHRD, refer to Compiling the Hardware Design and Integrating U-boot FSBL.

2. Start Quartus Prime Pro and open Quartus project ghrd_1sx280lu2f50e2vgs2.qpf

3. In Quartus, start Platform Designer by going to Tools → Platform Designer.

4. The tool will ask to select a file to open. Select the file ~/s10_soc_devkit_ghrd/qsys_top.qsys and click Open.

5. Platform Designer will load the file, displaying a progress bar. Once file is loaded, Platform Designer will display the system.

6. Locate the "emif_hps" component. Double click to open the parameter window

7. In the Memory tab:

• (for 72-bit width design) change the DQ width from 64 to 72
  
• (for 40-bit width design) change the DQ width from 64 to 40
  

8. In the Controller tab, tick the checkbox for Enable Error Detection and Correction Logic with ECC. If you need auto correction for single bit errors, tick the checkbox for Enable Auto Correction to External Memory.

9. Save the qsys_top.qsys file once done.

Updating Top Level verilog file

Whenever ECC is enabled, the physical databus must be expanded to accommodate the ECC channel. As such, the GHRD design will need to be updated to accommodate the changes.

1. Return to the Quartus main window and open the top level file ghrd_s10_top.v

2. Change the width for the following ports:

• For 72-bit width design:
  • emif_hps_mem_mem_dq from 64 to 72
  • emif_hps_mem_mem_dbi_n from 8 to 9
  • emif_hps_mem_mem_dqs from 8 to 9
  • emif_hps_mem_mem_dqs_n from 8 to 9

• For 40-bit width design:
  • emif_hps_mem_mem_dq from 64 to 40
    
  • emif_hps_mem_mem_dbi_n from 8 to 5
  • emif_hps_mem_mem_dqs from 8 to 5
    
  • emif_hps_mem_mem_dqs_n from 8 to 5
    

3. Save the ghrd_s10_top.v file once done

Updating Device Pin Assignment

The ECC-enabled design has different pin assignments compared to the GHRD, hence we need to update the default pin assignments.

1. In the project directory, open ghrd_1sx280lu2f50e2vgs2.qsf file using text editor

2. For 72-bit design, add the following pin assignments to this file

#Add additional location assignments for 72-bit width
set_location_assignment PIN_R32 -to emif_hps_mem_mem_dqs[8]
set_location_assignment PIN_T32 -to emif_hps_mem_mem_dqs_n[8]
set_location_assignment PIN_U34 -to emif_hps_mem_mem_dbi_n[8]
set_location_assignment PIN_T34 -to emif_hps_mem_mem_dq[64]
set_location_assignment PIN_R31 -to emif_hps_mem_mem_dq[65]
set_location_assignment PIN_U33 -to emif_hps_mem_mem_dq[66]
set_location_assignment PIN_T31 -to emif_hps_mem_mem_dq[67]
set_location_assignment PIN_R34 -to emif_hps_mem_mem_dq[68]
set_location_assignment PIN_U32 -to emif_hps_mem_mem_dq[69]
set_location_assignment PIN_V32 -to emif_hps_mem_mem_dq[70]
set_location_assignment PIN_P33 -to emif_hps_mem_mem_dq[71]

For 40-bit design, firstly delete the existing assignments for emif_hps_mem_mem_dq[32] to emif_hps_mem_mem_dq[63]. Then update the new location assignments for emif_hps_mem_mem_dqs[4], emif_hps_mem_mem_dqs_n[4] and emif_hps_mem_mem_dbi_n[4] as shown below. Lastly, add the rest of the 8-bit ECC location assignments:

#For 40-bit width, comment out or delete default location assignment for the three signals below
#set_location_assignment PIN_T26 -to emif_hps_mem_mem_dqs[4]
#set_location_assignment PIN_R27 -to emif_hps_mem_mem_dqs_n[4]
#set_location_assignment PIN_N25 -to emif_hps_mem_mem_dbi_n[4]

#Update new location assignment
set_location_assignment PIN_R32 -to emif_hps_mem_mem_dqs[4]
set_location_assignment PIN_T32 -to emif_hps_mem_mem_dqs_n[4]
set_location_assignment PIN_U34 -to emif_hps_mem_mem_dbi_n[4]

#Lastly, add in new 8-bit ECC location assignments.
#Remember to delete the default location assignments for emif_hps_mem_mem_dq[32] to emif_hps_mem_mem_dq[63]
set_location_assignment PIN_T34 -to emif_hps_mem_mem_dq[32]
set_location_assignment PIN_R31 -to emif_hps_mem_mem_dq[33]
set_location_assignment PIN_U33 -to emif_hps_mem_mem_dq[34]
set_location_assignment PIN_T31 -to emif_hps_mem_mem_dq[35]
set_location_assignment PIN_R34 -to emif_hps_mem_mem_dq[36]
set_location_assignment PIN_U32 -to emif_hps_mem_mem_dq[37]
set_location_assignment PIN_V32 -to emif_hps_mem_mem_dq[38]
set_location_assignment PIN_P33 -to emif_hps_mem_mem_dq[39]

3. Save the file once done

Compiling Hardware Design

1. Once you have completed the required changes in both Platform Designer and Quartus main window, you need to recompile the hardware design.

2. In Platform Designer, click the "Sync System Infos", then "Validate System Integrity" and "Reload and Update All Components" to refresh the IP. Then click the Generate HDL ... button on the bottom right corner. The Generation window will open. Click Generate button on bottom right corner.

3. Platform Designer will generate the system, displaying a progress bar.

4. Once complete, Platform Designer will display the "Generate Completed" message. Click Close to close the Generate window and get back to main Platform Designer window.

5. Close the Platform Designer window and return to main Quartus window.

6. In Quartus, start a compilation by going to Processing → Start Compilation. Then Quartus will compile the project

7. When compilation is completed, Quartus will display the status.

The following will be created:

• ~/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vgs2.sof - FPGA configuration file with HPS handoff data

Updating U-boot FSBL and SSBL

Compiling U-boot FSBL and SSBL

Note: Future revision of SoC EDS will include the U-boot source code that support ECC, hence this step will no longer apply.

To compile U-boot that support ECC, follow the steps at Compiling U-Boot FSBL and SSBL except that you need to retrieve the U-boot source code from Intel Public Repository in Step 3.

Once the compilation is completed, you will obtain the following files:

File	Description
u-boot	U-Boot SSBL ELF file
u-boot-dtb.bin	U-Boot SSBL binary file
u-boot-dtb.img	U-Boot SSBL image file
u-boot-spl-dtb.bin	U-Boot FSBL binary file (in spl subfolder)

Updating the U-boot FSBL

1. Convert the U-boot FSBL to ihex using the command:

$ aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.ihex

2. Then, integrate the hex file into the .sof file using the following command:

$ quartus_cpf --bootloader=software/u-boot/spl/u-boot-spl-dtb.ihex output_files/ghrd_1sx280lu2f50e2vgs2.sof output_files/ghrd_1sx280lu2f50e2vgs2_hps.sof

This will create the file ghrd_1sx280lu2f50e2vgs2_hps.sof that contains the FPGA configuration info, as well as the HPS U-boot FSBL code and HPS FSBL hardware Handoff binary.

Updating U-boot SSBL

1. Insert the HPS SD Card into the host PC, and mount the card in the OS filesystem.

2. Locate the file u-boot-dtb.img stored in the FAT partition of the SD Card. Replace this file with the u-boot-dtb.img file compiled from the step above.

3. Safely eject the SD Card and insert the card back into the micro SD card slot on the HPS Daughter Card

Convert Programming File to JIC

The Stratix 10 SoC device can receive the initial configuration bitstream from either:

• JTAG via Quartus Prime Programmer
• SDM QSPI

Quartus Prime Programmer can program the device (via JTAG) using the ghrd_1sx280lu2f50e2vgs2_hps.sof file generated from earlier step. Upon successful programming via JTAG, the HPS will execute FSBL code located on the HPS on-chip memory.

If SDM QSPI is to be used instead, you need to first convert the ghrd_1sx280lu2f50e2vgs2_hps.sof to jic file. To do this, use the following command:

$ quartus_cpf -c -s 1SX280LU2S2 -d MT25QU02G output_files/ghrd_1sx280lu2f50e2vgs2_hps.sof output_files/ghrd_1sx280lu2f50e2vgs2_hps.jic

Using Quartus Prime Programmer, you can then program the jic file to the SDM QSPI. Refer to the Booting Linux with Pre-built SD Card Image link for steps to perform this operation.

Sample Boot Up Console Output

Below is the example of output displayed from the serial console when the device boots up with ECC enabled. The portion when ECC is being initialized is intentionally set to bold for clarity.

Sample output for 72-bit width design:

U-Boot SPL 2017.09-00093-g1c74e1d (May 03 2018 - 15:31:41)
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: Initializing Hard Memory Controller
DDR: Calibration success
SDRAM: Initializing ECC 0x00000000 - 0x80000000
SDRAM-ECC: Initialized success with 1343 ms
DDR: HMC init success
DDR: 2048 MiB
DDR: Running SDRAM size sanity check
DDR: SDRAM size check passed!
QSPI: Reference clock at 200000000 Hz
Trying to boot from MMC1
reading u-boot-dtb.img
reading u-boot-dtb.img

U-Boot 2017.09-00093-g1c74e1d (May 03 2018 - 15:31:41 +0800)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform
FPGA:  Intel FPGA Stratix 10
Model: Intel SOCFPGA Stratix 10 SoC Development Kit
DRAM:  1 GiB
MMC:   dwmmc0@0xff808000: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Intel SOCFPGA Stratix 10 SoC Development Kit
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 36:07:2b:b9:65:5b
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
SOCFPGA_STRATIX10 #

Sample output for 40-bit width design:

U-Boot SPL 2017.09-00093-g1c74e1d (May 03 2018 - 15:31:41)
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: Initializing Hard Memory Controller
DDR: Calibration success
SDRAM: Initializing ECC 0x00000000 - 0x40000000
SDRAM-ECC: Initialized success with 671 ms
DDR: HMC init success
DDR: 1024 MiB
DDR: Running SDRAM size sanity check
DDR: SDRAM size check passed!
QSPI: Reference clock at 200000000 Hz
Trying to boot from MMC1
reading u-boot-dtb.img
reading u-boot-dtb.img

U-Boot 2017.09-00093-g1c74e1d (May 03 2018 - 15:31:41 +0800)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform
FPGA:  Intel FPGA Stratix 10
Model: Intel SOCFPGA Stratix 10 SoC Development Kit
DRAM:  1 GiB
MMC:   dwmmc0@0xff808000: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Intel SOCFPGA Stratix 10 SoC Development Kit
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - b6:b4:31:10:a7:a7
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
SOCFPGA_STRATIX10 #