Introduction

The GSRD (Golden System Reference Design) provides a set of essential hardware and software system components that can be used as a starting point for various custom user designs.

Getting Started Guides

• Compiling the U-boot FSBL and SSBL
• Compiling the Hardware Design and Integrating U-boot FSBL
• Compiling Angstrom Linux Distribution
• Creating and Updating the SD Card
• Booting Linux Using SD Card Image
• Running Sample Linux Applications
• Connecting to Board Web Server and SSH Client

Customizing the Stratix 10 GSRD

• Enabling ECC for HPS SDRAM (applies to v18.0 only)
• Configuring FPGA from HPS with HPS boot first mode
• Adapting HPS EMAC to SGMII Interface
• Single QSPI Flash Boot (FPGA First)
• Single QSPI Flash Boot (HPS First)
• Using eMMC as HPS Storage
• Using NAND as HPS Storage
• Secure Boot Demo Design
• Partial Reconfiguration with HPS
• PCIe Root Port with MSI
• Routing SPI Peripheral to FPGA
• Stratix 10 with 10Gbe supporting IEEE1588 PTP

GSRD Overview

The S10 GSRD consists of:

• Stratix 10 SoC Development Kit, ES Edition
• Golden Hardware Reference Design (GHRD)
• Linux release
• Linux sample drivers
• Linux sample applications

Release Notes, Release Contents, Locations and Release Tags

The latest release notes, contents and tags can be found here:

Release Notes, Contents, Locations and Tags

Prerequisites

The following are required in order to be able to fully exercise the S10 GSRD:

• Stratix 10 SoC Development Kit, ES Edition
• Host PC running Linux (CentOS 6.6 was tested to work)
• Intel SoC EDS Pro Edition v18.0 and above
• Intel Quartus™ Prime Pro Edition v18.0 and above

Note that the First-Stage and Second-Stage Bootloader (U-Boot) compilation requires a Linux host PC. The rest of the operations can be performed on either a Windows or Linux host PC.

GHRD Overview

See GHRD Overview.

Build Flow

The following diagram illustrates the full build flow for the GSRD.

s10buildflow

The following table presents the tools that are used in the build flow:

Tool	Description	Part of
Quartus Prime Pro	Create, edit and compile FPGA hardware designs	Intel Quartus Prime Pro
Quartus Prime Convert Programming File	Utility that merge FSBL into sof file, and also create jic file	^
Quartus Programmer	Perform JTAG programming to FPGA and flash programming on SDM QSPI	Both Intel Quartus Prime Pro and SoC EDS
U-boot makefile	Generate U-boot FSBL and SSBL	SoC EDS
Arm DS-5 Intel SoC FPGA Edition	Software Development Suite	^

The following table describes the output files of the build flow diagram:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
.hex	Hexadecimal source file - contains FSBL content
.sof + Handoff and FSBL	SRAM Object File that embed the hardware design information and HPS FSBL content
.jic	JTAG indirect programming file - used for programming of the SDM QSPI

Not all the people involved in a project need to deal with the full flow. For example:

• Board Designer: Typically works with the hardware engineer to decide the design of the custom board, pin muxing, HPS peripherals and muxing.
• Hardware Engineer: Usually works only on the FPGA Quartus Project, and notifies the firmware engineer whenever the hardware files (.sof) were changed. He also needs to notify the firmware engineer of any hardware interface changes.
• Firmware Engineer: Typically updates the Linux drivers according to the changes that were performed in hardware, recompiles the kernel if necessary.
• Software Engineer: Develops the applications that run on top of the Linux OS. May need to change the software when new drivers are added.

Stratix 10 HPS Boot Flow

The Stratix 10 Golden System Reference Design (GSRD) User Manuals boot flow includes the following stages:

1. SDM
2. First-Stage Bootloader (FSBL) U-Boot
3. Second-Stage Bootloader (SSBL) U-Boot
4. Operating System (OS)
5. Application

s10bootflow

The following table presents a short description of the different boot stages:

Stage	Description
SDM	Performs configuration, loads FSBL to HPS OCRAM and release HPS from reset
FSBL	Initializes the HPS and configures basic functions such as HPS Dedicated I/O
SSBL	Enables more hardware such as EMAC and loads OS onto HPS SDRAM
OS	Operating System such as Linux
Application	User application in the system

For more information about Stratix 10 SoC booting please refer to Stratix 10 Hard Processor System Technical Reference Manual, Booting and Configuration chapter.