Creating the U-boot script

Overview

This page shows the steps to create a U-boot script in case any additional changes are required. Otherwise the existing U-boot script can be used as-is.

The U-boot script file can be executed by the U-boot Second-Stage Bootloader (SSBL) to perform additional task such as modifying register values and enabling HPS-to-FPGA bridges. You can create the script by firstly using a text editor to enter the commands, and then creating a .scr file using mkimage tool (included with Intel SoC EDS)

U-boot Script Template

Shown below is the example of a U-boot script and its usage. You can modify the content of the template to suit your design requirement:

A simple u-boot script template is shown below:

#-The MIT License (MIT) 
#-Copyright © 2018 Intel Corporation 
# 
#-Permission is hereby granted, free of charge, to any person obtaining a copy 
#-of this software and associated documentation files (the "Software"), to deal 
#-in the Software without restriction, including without limitation the rights 
#-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
#-copies of the Software, and to permit persons to whom the Software is 
#-furnished to do so, subject to the following conditions: 
# 
#-The above copyright notice and this permission notice shall be included in 
#-all copies or substantial portions of the Software. 
# 
#-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
#-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
#-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
#-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
#-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
#-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
#-SOFTWARE. 
# 
#-Run bridge enable command
bridge enable;
#
#-Enable the F2SDRAM[012] in the DDR scheduler sideband manager 
mw 0xF8024050 0x00000092;
#
#-Setting the region address limit for FPGA2SDRAM0
mw 0xF8020228 0x3FFFFFF;
#
#-Enable the SDRAM L3 interconnect F2SDRAM0 firewall region0 
mw 0xF8020204 0x00000002
#
#-Set the privilege filter bits for the H2F and LWH2F bridges and everything 
mw 0xFFD24800 0xFFFFFFFF

The u-boot script can also be used to set various NOC firewall registers. You can refer to below for a more comprehensive template that does this.

#-The MIT License (MIT) 
#-Copyright © 2018 Intel Corporation 
# 
#-Permission is hereby granted, free of charge, to any person obtaining a copy 
#-of this software and associated documentation files (the "Software"), to deal 
#-in the Software without restriction, including without limitation the rights 
#-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
#-copies of the Software, and to permit persons to whom the Software is 
#-furnished to do so, subject to the following conditions: 
# 
#-The above copyright notice and this permission notice shall be included in 
#-all copies or substantial portions of the Software. 
# 
#-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
#-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
#-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
#-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
#-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
#-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
#-SOFTWARE. 
# 
#-Run bridge enable command
bridge enable;
#
#-Set the privilege filter bits for the H2F and LWH2F bridges and everything 
mw.l 0xFFD24800 0xFFFFFFFF; 
#
#-Clear the disable bit, F2H access 
mw.q 0xF70105A0 0x0000000000000000; 
#
#-Clear the non-secure and privileged valid bits, F2H access 
mw.q 0xF7010668 0x000000fffffc0000; 
#
#-Enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu) to system manager space
mw.l 0xFFD2115C 0x01010001; 
#
#-Configure the SDRAM L3 interconnect F2SDRAM0 firewall region0 registers 
mw.l 0xF8020210 0x00000000; 
mw.l 0xF8020214 0x00000000; 
mw.l 0xF8020218 0x3FFFFFFF; 
mw.l 0xF802021C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM0 firewall region0 
mw.l 0xF8020204 0x00000001; 
#
#-Configure the SDRAM L3 interconnect F2SDRAM1 firewall region0 registers 
mw.l 0xF8020310 0x00000000; 
mw.l 0xF8020314 0x00000000; 
mw.l 0xF8020318 0x3FFFFFFF; 
mw.l 0xF802031C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM1 firewall region0 
mw.l 0xF8020304 0x00000001; 
#
#-Configure the SDRAM L3 interconnect F2SDRAM2 firewall region0 registers 
mw.l 0xF8020410 0x00000000; 
mw.l 0xF8020414 0x00000000; 
mw.l 0xF8020418 0x3FFFFFFF; 
mw.l 0xF802041C 0x00000000; 
#
#-Enable the SDRAM L3 interconnect F2SDRAM2 firewall region0 
mw.l 0xF8020404 0x00000001; 
#
#-Enable the F2SDRAM[012] in the DDR scheduler sideband manager 
mw.l 0xF8024050 0x00000092; 
#
#-Release the 3xF2S, F2H, H2F and LWH2F bridges from reset 
mw.l 0xFFD1102C 0x00000000;

Once you have completed the entries to the file, save it as .txt extension (for example, u-boot.txt)

Converting to .scr file

To convert the .txt file to .scr file, firstly launch the SoC EDS command shell. Then, run the following command:

$ mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "My script" -d u-boot.txt u-boot.scr

*Note:* mkimage tool is only included in the Linux version of Intel SoC EDS.

The mkimage tool will append the input text file with U-boot image header required by the U-boot SSBL, and save the output as .scr file (u-boot.scr in the example above).