Overview

By default, the SSBL only brings all of the bridges out of reset. It does not automatically configure or enable the bridges. You must specifically configure and enable all of the bridges according to your own design. This can be accomplished by creating a “u-boot.scr” script file that is executed by the SSBL, where the SSBL modifies any registers necessary to configure the bridges. At this point the bridges are configured and enabled, and will not be changed by the SSBL, even during any future FPGA configurations.

Example Script (u-boot.scr)

 

#-The MIT License (MIT) 
#-Copyright © 2018 Intel Corporation 
# 
#-Permission is hereby granted, free of charge, to any person obtaining a copy 
#-of this software and associated documentation files (the "Software"), to deal 
#-in the Software without restriction, including without limitation the rights 
#-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 
#-copies of the Software, and to permit persons to whom the Software is 
#-furnished to do so, subject to the following conditions: 
# 
#-The above copyright notice and this permission notice shall be included in 
#-all copies or substantial portions of the Software. 
# 
#-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
#-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
#-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
#-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
#-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
#-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
#-SOFTWARE. 
# 

#-Set the privilege filter bits for the H2F and LWH2F bridges and everything 
mw.l 0xFFD24800 0xFFFFFFFF 

#-Clear the disable bit, F2H access 
mw.q 0xF70105A0 0x0000000000000000 

#-Clear the non-secure and privileged valid bits, F2H access 
mw.q 0xF7010668 0x000000fffffc0000 

#-Enable non-secure F2H transactions to access the system manager space 
#-commented out as u-boot appears to set this by default for us now 
#-mw.l 0xFFD2115C 0x00010000 

#-Configure the SDRAM L3 interconnect F2SDRAM0 firewall region0 registers 
mw.l 0xF8020210 0x00000000 
mw.l 0xF8020214 0x00000000 
mw.l 0xF8020218 0x3FFFFFFF 
mw.l 0xF802021C 0x00000000 

#-Enable the SDRAM L3 interconnect F2SDRAM0 firewall region0 
mw.l 0xF8020204 0x00000001 

#-Configure the SDRAM L3 interconnect F2SDRAM1 firewall region0 registers 
mw.l 0xF8020310 0x00000000 
mw.l 0xF8020314 0x00000000 
mw.l 0xF8020318 0x3FFFFFFF 
mw.l 0xF802031C 0x00000000 

#-Enable the SDRAM L3 interconnect F2SDRAM1 firewall region0 
mw.l 0xF8020304 0x00000001 

#-Configure the SDRAM L3 interconnect F2SDRAM2 firewall region0 registers 
mw.l 0xF8020410 0x00000000 
mw.l 0xF8020414 0x00000000 
mw.l 0xF8020418 0x3FFFFFFF 
mw.l 0xF802041C 0x00000000 

#-Enable the SDRAM L3 interconnect F2SDRAM2 firewall region0 
mw.l 0xF8020404 0x00000001 

#-Enable the F2SDRAM[012] in the DDR scheduler sideband manager 
mw.l 0xF8024050 0x00000092 

#-Release the 3xF2S, F2H, H2F and LWH2F bridges from reset 
mw.l 0xFFD1102C 0x00000000