Solectrix SMARC compliant System-on-Module

SXoM-C5 is a complete System-on-Module (SoM) compliant with the SMARC (Smart Mobility ARChitecture) specification by SGET. The board is designed to function as the System core of modular platforms for high-Performance DSP applications.

Key Features

• Low-power embedded architecture
• High-performance data processing
• Ultra-compact form factor: 82 mm x 50 mm
• System-on-Module compliant with SMARC specification by SGET

• Powered by Altera Cyclone V SX SoC 5CSX C2/C4/C5/C6 (customer-specific)
• Cyclone V FPGA fabric
• ARM-based hard processor system
• 8 Gb DDR3 SDRAM ×32 bit (CPU)
• 8 Gb DDR3 SDRAM ×32 bit (FPGA)

FPGA Fabric Features

• Altera Cyclone V FPGA fabric
• 25K – 110K logic elements
• 1.4 – 5.6 Mb block memory
• 36 – 112 DSP blocks

CPU Features

• Dual-core ARM Cortex™-A9 MPCore™ processor, 700 – 925 MHz clock frequency
• 4,625 DMIPS (Dhrystone 2.1) at 925 MHz (two cores)
• 32 KB of L1 instruction cache and 32 KB of L1 data cache per processor
• 512 KB of shared L2 cache
• 64 KB of on-chip RAM

Product Webpage
http://www.fpga.sx/system-on-a-chip-sxom-c5.html

Datasheet
http://www.fpga.sx/pdf/SXoM-C5.pdf

SXoM-C5 is a complete System-on-Module (SoM) compliant with the SMARC (Smart Mobility ARChitecture) specification by SGET. The board is designed to function as the System core of modular platforms for high-Performance DSP applications.

Key Features

• Low-power embedded architecture
• High-performance data processing
• Ultra-compact form factor: 82 mm x 50 mm
• System-on-Module compliant with SMARC specification by SGET

• Powered by Altera Cyclone V SX SoC 5CSX C2/C4/C5/C6 (customer-specific)
• Cyclone V FPGA fabric
• ARM-based hard processor system
• 8 Gb DDR3 SDRAM ×32 bit (CPU)
• 8 Gb DDR3 SDRAM ×32 bit (FPGA)

FPGA Fabric Features

• Altera Cyclone V FPGA fabric
• 25K – 110K logic elements
• 1.4 – 5.6 Mb block memory
• 36 – 112 DSP blocks

CPU Features

• Dual-core ARM Cortex™-A9 MPCore™ processor, 700 – 925 MHz clock frequency
• 4,625 DMIPS (Dhrystone 2.1) at 925 MHz (two cores)
• 32 KB of L1 instruction cache and 32 KB of L1 data cache per processor
• 512 KB of shared L2 cache
• 64 KB of on-chip RAM

Product Webpage
http://www.fpga.sx/system-on-a-chip-sxom-c5.html

Datasheet
http://www.fpga.sx/pdf/SXoM-C5.pdf