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SoCEDS and ARM Development Studio

30 November 2023 - 15:20 | | Version 66 | | Arm DS, Bare-metal, SoC EDS, SoC FPGA
WARNING: SoC EDS is a discontinued product, which is no longer supported. The information in this page is provided for archival purposes only!
For up to date information about HWLIBs please see Hardware Library (HWLibs).

Introduction

This page presents some details about SoC EDS 20.1 Pro and Standard releases:
  • Installing the tools
  • Running the tools
  • Licensing
  • Arria 10 Bare-metal Example using 20.1 Pro
  • Cyclone V Bare-metal Example using 20.1 Std

The most important changes in SoC EDS 20.1 are:
  • Arm DS-5 is not automatically installed with SoC EDS.
  • Users need to download and install Arm DS separately. Arm DS is the successor of Arm DS-5 and offers similar functionality.
  • Mentor bare-metal toolchain for Cortex-A9 is not installed with SoC EDS
  • Users need to download and install Linaro bare-metal toolchain for Cortex-A9 separately. It offers similar functionality with Mentor bare-metal toolchain.
  • Arria 10 HWLIBs bare-metal timer example was updated to
    • Use either the Linaro or Arm compiler
    • Use either OCRAM or DDR memory
    • Use either semihosting or UART for console
    • Copy all relevant HWLIBs files in the project. This allows easy customization of HWLIBs source code without changing the master copy inside SoC EDS.

The SoC EDS User Guide will be updated at a later date.

Installation

The installation process consists of the following steps:
  • Download and install SoC EDS
  • Download and install Arm DS
  • Download and install Linaro bare-metal toolchain

In addition to the above, the following need to be installed on Windows machines:
  • Cygwin - offers a Linux-like enviornment on Windows, and is required by the Embedded Command Shell
  • MinGW - used as a platform to build the Newlib library used by the Linaro bare-metal toolchain.

Installation Folders

The default installation folder for SoC EDS, referred to as <SoC FPGA EDS installation directory> is shown in the table below:

Version Host OS Folder
Standard Linux ~/intelFPGA/20.1/embedded
^ Windows C:\intelFPGA\20.1\embedded
Professional Linux ~/intelFPGA_pro/20.1/embedded
^ Windows C:\intelFPGA_pro\20.1\embedded

The default installation folder for the Intel Quartus Prime Programmer, referred to as <Quartus Prime installation directory> is shown in the table below:

Version Host OS Folder
Standard Linux ~/intelFPGA/20.1/qprogrammer
^ Windows C:\intelFPGA\20.1\qprogrammer
Professional Linux ~/intelFPGA_pro/20.1/qprogrammer
^ Windows C:\intelFPGA_pro\20.1\qprogrammer

The default installation folder for Arm DS Intel SoC FPGA Edition is presented in the table below:

Host OS Folder
Linux /opt/arm/developmentstudio-2020.1
Windows c:Program Files/Arm/Development Studio 2020.0\

Linux

Install SoC EDS

Note: the screenshots taken in this section are for the Pro version of SoC EDS, but the procedure is similar for the Std version.

1. Download and run the SoC EDS Installer from https://fpgasoftware.intel.com/soceds/. Current version is 20.1 and the filenames are:
  • For 20.1 Pro: SoCEDSProSetup-20.1.0.177-linux.run
  • For 20.1 Std: SoCEDSSetup-20.1.0.711-linux.run

Click Next on the welcome screen.

2. Select I accept the agreement and click Next.

3. Leave the default installation path (or change it if you need it somewhere else) and click Next

4. Leave the Quartus Programmer selected (unless you already have full Quartus installed) and click Next

5. Review the summary and click Next

6. The tools will be installed

7. The Programmer will also be installed (if selected).

8. Installation will finish.

Install ARM DS

1. Download Arm DS installer archive from https://fpgasoftware.intel.com/armds/. Current version is 20.1 and the filename is called DS000-BN-00001-r20p1-00rel1.tgz.

2. Extract the archive and run the installer as root 

tar xf DS000-BN-00001-r20p1-00rel1.tgz
cd DS000-BN-00001-r20p1-00rel1/
sudo ./armds-2020.1.sh

3. The installer will show the licensing agreement. Scroll using the spacebar until the end of the license the type "yes" and press Enter 

Please answer with one of: 'yes' or 'no/quit'
Do you agree to the above terms and conditions? yes

4. Press Enter to run the platform requirements check. 

Please answer with one of: 'yes/y' or 'no/n'
Run installation platform requirement checks? [default: yes] 
--- Running installation platform requirement checks
Running dependency check [succeeded]

5. Leave the default installation path (unless you want to change it) and press Enter. 

Where would you like to install to? [default: /opt/arm/developmentstudio-2020.1]

6. Press Enter to allow the new folder to be created: 

Please answer with one of: 'yes/y' or 'no/n'
'/opt/arm/developmentstudio-2020.1' does not exist, create? [default: yes] 
--- Installing to '/opt/arm/developmentstudio-2020.1' (This may take a while...)

7. Press Enter to allow the dektop menus to be added. 

Please answer with one of: 'yes/y' or 'no/n'
Install desktop menu item additions? [default: yes] 
--- Installing menu entries

8. Press Enter to allow the drivers to be installed. 

Post install stage provides the following functions:
- Installation of USB drivers for RealView ICE and DSTREAM hardware units
Please answer with one of: 'yes/y' or 'no/n'
Run post install setup scripts? [default: yes] 
--- Running post install setup scripts

9. Succesfull installation will result in the following message: 

-----------------------------------
Installation completed successfully
-----------------------------------

To start using Arm Development Studio 2020.1 either:
- Create a suite sub-shell using /opt/arm/developmentstudio-2020.1/bin/suite_exec 
- Launch GUI tools via their desktop menu entries

The Release notes for the product can be found here: file:///opt/arm/developmentstudio-2020.1/sw/info/readme.html

Install Linaro Bare-metal Toolchain

This section shows how to install the Linaro bare-metal toolchain for Cortex-A9, useful for compiling bare-metal programs for Cyclone V SoC, Arria V SoC and Arria 10 SoC devices.

1. Start an Embedded Command Shell 

~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh

2. Change current folder to linaro and run the installation script 

cd $SOCEDS_DEST_ROOT/host_tools/linaro/
./install_linaro.sh

3. Upon succesfull completion, the following will be installed in the $SOCEDS_DEST_ROOT/host_tools/linaro/ folder:
  • gcc - GCC Compiler
  • newlib - Newlib library

Windows

Install SoC EDS

Note: the screenshots taken in this section are for the Pro version of SoC EDS, but the procedure is similar for the Std version.

1. Download and run the SoC EDS Installer from https://fpgasoftware.intel.com/soceds/. Current version is 20.1 and the filenames are:
  • For 20.1 Pro: SoCEDSProSetup-20.1.0.177-windows.exe
  • For 20.1 Std: SoCEDSSetup-20.1.0.711-windows.exe

2. Select I accept the agreement and click Next.

3. Leave the default installation path (or change it if you need it somewhere else) and click Next

4. Leave the Quartus Programmer selected (unless you already have full Quartus installed) and click Next

5. Review the summary and click Next

6. The tools will be installed

7. The Programmer will also be installed (if selected).

8. Installer will ask confirmation for driver installation. Leave them checked and press Finish.

9. Accept all defaults to install the USB Blaster drivers.

10. Accept all defaults to install FTDI CDM drivers (used to connect to USB serial ports on Development Kits).

Install ARM DS

1. Download Arm DS installer archive from https://fpgasoftware.intel.com/armds/. Current version is 20.1 and the filename is called DS000-BN-00000-r20p1-00rel1.zip.

2. Extract the archive and run the DS000-BN-00000-r20p1-00rel1\armds-2020.1.exe installer.

3. Press Next on the welcome screen.

4. Check I accept the terms in the License Agreement and press Next.

5. Leave the default installation location (or change it if desired) and press Next.

6. Press Install to proceed with installation.

7. Tool will be installed.

8. Press Next on the driver installation welcome screen.

9. Accept all default options for driver installation.

10. Installation will be completed. Press Finish.

Install Cygwin

1. Go to https://cygwin.com/ and download the installer (https://cygwin.com/setup-x86_64.exe) to your computer.

2. Start a Command Prompt as an administrator

3. Change the current directory to cygwin_setup

For 20.1 Pro: 
cd c:\intelFPGA_pro\20.1\embedded\cygwin_setup\
For 20.1 Std: 
cd c:\intelFPGA\20.1\embedded\cygwin_setup\

4. Run the soceds-cygwin-setup.bat executable, passing it the full path to where you downloaded the setup-x86_64.exe installer (in the example below it was downloaded in user's 'Downloads' folder): 

soceds-cygwin-setup.bat %USERPROFILE%\Downloads\setup-x86_64.exe

5. The installer application will start.

6. The installer application will complete.

Install MingGW

1. Go to http://www.mingw.org/wiki/Getting_Started, then download and run the https://osdn.net/projects/mingw/downloads/68260/mingw-get-setup.exe installer as an administrator

2. Installer application will start, press Install.

3. Leave the default settings, then press Continue.

4. Press Continue again to proceed.

5. In Basic Setup view, click on mingw-developer-toolkit-bin and mingw32-base-bin and msys-base-bin and select Mark for Installation.

6. In the All Packages view, click on msys-wget-bin and select Mark for Installation.

7. Select Installation > Apply Changes from the top menu.

8. Click Apply to proceed.

9. Installer will download all necessary packages.

10. After installer applied all changes, click Close.

11. Select Installation > Quit from the top menu

Install Linaro Bare-metal Toolchain

This section shows how to install the Linaro bare-metal toolchain for Cortex-A9, useful for compiling bare-metal programs for Cyclone V SoC, Arria V SoC and Arria 10 SoC devices. 1. Run C:\MinGW\msys\1.0\msys.bat as an administrator.

2. In the Msys console, go to linaro folder:

For 20.1 Pro: 
cd c:/intelFPGA_pro/20.1/embedded/host_tools/linaro
For 20.1 Std: 
cd c:/intelFPGA/20.1/embedded/host_tools/linaro

3. Run the installer: 

./install_linaro.sh

4. Linaro toolchain will be downloaded, and newlib library will be downloaded and compiled.

5. Upon succesfull completion, the following will be installed in the linaro folder:
  • gcc - GNU Compiler
  • newlib - Newlib library

Running the Tools

The tools provided with SoC EDS need to be ran from an Embedded Command Shell. Additionally, the Arm DS tools need to be run from an Arm DS shell.

Linux

Starting Embedded Command Shell

For 20.1 Pro: 
~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh
For 20.1 Std: 
~/intelFPGA/20.1/embedded/embedded_command_shell.sh

Starting Arm DS Shell

1. Start an Embedded Command Shell

For 20.1 Pro: 
~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh
For 20.1 Std: 
~/intelFPGA/20.1/embedded/embedded_command_shell.sh

2a. If Arm Compiler 5 is desired: 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 5" bash

2b. If Arm Compiler 6 is desired (only needed by the 20.1 Pro): 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 6" bash

Starting Arm DS Eclipse

1. Start an Embedded Command Shell

2. Start an Arm DS Shell with the desired compiler selected

3. Run the armds_ide command.

Helpful parameters for armds_ide command are:
  • -nosplash: speeds up loading by not displaying the splash screen
  • -data <workspace-name>: allows the workspace folder to be specified

Windows

Starting Embedded Command Shell

You can start an Embedded Command Shell by going to

For 20.1 Pro: Start menu > Intel FPGA 20.1 Pro Edition > SoC EDS Command Shell.
For 20.1 Std: Start menu > Intel FPGA 20.1 > SoC EDS Command Shell.

Starting Arm DS Shell

1. Start an Embedded Command Shell

2. Run the cmdsuite program 

/cygdrive/c/Program\ Files/Arm/Development\ Studio\ 2020.0/bin/cmdsuite.exe

3. Run the bash program to get back to Embedded Command Shell colors.

4. If needed, run the select_toolchain command to select between Arm Compiler 5 and Arm Compiler 6

Starting Arm DS Eclipse

1. Start an Embedded Command Shell

2. Start an Arm DS Shell with the desired compiler selected

3. Run the armds_ide command.

Helpful parameters for armds_ide command are:
  • -nosplash: speeds up loading by not displaying the splash screen
  • -data <workspace-name>: allows the workspace folder to be specified

SoC EDS Licensing

The only SoC EDS component which requires a license is the Arm DS Intel SoC FPGA Edition. Two license options are available:
  • Arm DS Intel SoC FPGA Edition License
  • 30-day Evaluation of Arm DS Intel SoC FPGA Edition License

Note: The 30-day Evaluation of Arm DS Intel SoC FPGA Edition License applies only to latest version of Arm DS, downloadable from https://developer.arm.com/tools-and-software/embedded/arm-development-studio/downloads

Refer to Arm DS Intel® SoC FPGA Edition Toolkit for details about DS features, and editions, including licensing.

Getting the License

Follow the steps below to get the License:

For Arm DS Intel SoC FPGA Edition License - If you have purchased a SoC development kit or a stand-alone license for DS Intel SoC FPGA Edition AE, then you have already received an Arm license serial number. This is a 15-digit alphanumeric string with two dashes in between. Use this serial number to activate your license in DS Intel SoC FPGA Edition, as shown in the "Activating the License" section.

For 30-Day Evaluation of DS-5 Intel SoC FPGA Edition License - If you want to evaluate the DS Intel SoC FPGA Edition, you can get a 30-Day Evaluation activation code by going to Arm DS Intel® SoC FPGA Edition Toolkit then clicking on Activate license code for Arm DS.

Activating the License

This section presents how to activate and apply the license.

1. Go to ARM Licensing Portal to generate a license file based on the license code you got with your Development Kit.

2. Start DS IDE

3. First time it is run it will ask you to add a product license. Select Add product license and click Next.

5. Select License File and browse to the place where you stored your generated license. Click Next.

6. The Arm Development Studio Intel FPGA Edition license will be selected. Click Next to activate it.

7. License will be activated. Click Finish to complete the process.

Arria 10 Bare Metal Example Using SoC EDS Pro Edition

This section contains instructions on running the Arria 10 Timer bare-metal example provided with SoC EDS. The example targets the Arria 10 SoC Development Kit.

The following are covered:
  • Configuring the FPGA: the FPGA needs to be configured first, to be able to bring up HPS DDR
  • Running U-Boot SPL: the SPL needs to be ran to initialize hardware and bring up HPS DDR
  • Exercise Application: importing, building and running the sample application
  • Customize sample application: change compiler, memory and semihosting options

The example was created on Linux, but it will work similarily on Windows. The only step that can only be performed on Linux is compiling U-Boot.

Configure FPGA

1. Start an Embedded Command Shell 

~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh

2. Configure FPGA with the SOF file included with SoC EDS: 

quartus_pgm -c 1 -m jtag -o "p;$SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof"

Build U-Boot

Note: U-Boot can only be built on Linux.

1. Start an Embedded Command Shell 

~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh

2. Build U-Boot 

# Generate U-Boot device tree
cd $SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/
rm -rf software/bootloader
mkdir -p software/bootloader
cd software/bootloader

# Get the U-Boot sourece code
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
git checkout -b test -t origin/socfpga_v2020.04

# Generate DTS include file based on the handoff file
./arch/arm/mach-socfpga/qts-filter-a10.sh \
../../../hps_isw_handoff/hps.xml \
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

# Build U-Boot
export CROSS_COMPILE=arm-eabi-
make socfpga_arria10_defconfig
make -j 24

The following files are created in $SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga:
  • spl/u-boot-spl - SPL executable
  • spl/u-boot-spl-dtb.bin - SPL device tree
  • u-boot - U-Boot executable
  • u-boot-dtb.bin - U-Boot device tree
  • u-boot-with-spl.sfp - flash image file with 4 x SPL + U-Boot image

3. Create SPL debug script 

cat <<EOT > $SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/software/bootloader/debug-spl.ds

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load spl and run up until the warm reset
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
thbreak *0x0
continue
wait 60s

# load spl again and run up until spl_boot_device
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
thbreak spl_boot_device
continue
wait 60s

EOT

4. Create U-Boot debug script 

cat <<EOT > $SOCEDS_DEST_ROOT/examples/hardware/a10_soc_devkit_ghrd/software/bootloader/debug-u-boot.ds

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load spl and run up until the warm reset
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
thbreak *0x0
continue
wait 60s

# load spl again and run up until spl_boot_device
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
thbreak spl_boot_device
continue
wait 60s

# load u-boot and run up to board_init_r
delete
loadfile \$sdir/u-boot-socfpga/u-boot
start 
wait
restore \$sdir/u-boot-socfpga/u-boot.dtb binary &_end
tbreak relocate_code
cont
wait 60s
symbol-file "\$sdir/u-boot-socfpga/u-boot" ((gd_t*)\$r9)->reloc_off
thbreak board_init_r
continue
wait 60s

EOT

Run U-Boot SPL from Debugger

U-Boot SPL needs to be run, in order to initialize the hardware based on the HPS settings in the Quartus project, and also bring up DDR. FPGA needs to be configured before this step.

1. Start an Embedded Command Shell 

~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh

2. Start a DS shell configured for Arm Compiler 5 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 5" bash

3. Start Arm DS IDE (Eclipse) 

armds_ide -data ~/ds.workspace&

4. In Eclipse Go to Run > Debug Configurations to open the Debug Configurations window

5. In the Debug Configurations window, select Generic Arm C/C++ Application, right click it and select New to create a new debug configuration

6. Rename the new configuration from “New_configuration” to “A10 SPL”

7. In Connection Tab:
  • Select target to be Intel SoC FPGA > Arria 10 SoC > Bare Metal Debug > Debug Cortex-A9_0
  • Select target connection to be USB-Blaster
  • Click Browse under Bare Metal Debug Connection and select the USB Blaster instance

8. In Debugger Tab:
  • Select Run control to be Connect Only
  • Check Run debug initialization debugger script, and click the File System icon near it to browse for the script ~/intelFPGA_pro/20.1/embedded/examples/hardware/a10_soc_devkit_ghrd/software/bootloader/debug-spl.ds
  • Click Debug button

9. Serial console will display that SPL ran fine and calibrated DDR successfully:

10. DS debugger will show SPL stopped on the spl_boot_device function

11. Exit the debugging section by pressing the red Disconnect from Target button

Exercise Sample Application

1. Start an Embedded Command Shell 

~/intelFPGA_pro/20.1/embedded/embedded_command_shell.sh

2. Start a DS shell configured for Arm Compiler 5 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 5" bash

3. Start Arm DS IDE (Eclipse) 

armds_ide -data ~/ds.workspace&

4. In Eclipse Go to File > Import > General > Existing Projects into Workspace and click Next

5. Check Select archive file then click Browse and go to ~/intelFPGA_pro/20.1/embedded/examples/software/Altera-SoCFPGA-HardwareLib-Timer-A10-GNU.tar.gz and click OK

6. Click Finish in the Import window.

7. The project is now imported.

8. Go to Project > Build to build the project

9. Go to Debug > Debug Configurations to open the Debug Configurations window.

10. In the Debug Configurations window, select the Altera-SoCFPGA-HardwareLib-Timer-A10-GNU-Debug configuration.

11. In the Debug Configurations window, Connection tab, click on the Browse button to select your USB Blaster instance.

12. In the Debug Configurations window click on Debug to start a debugging session.

13. The debugger will download the sample application executable on the board, and run it up to the main function. Click on the green Continue button, or press F8 to let the application run.

14. The application will run to completion, toggling LEDs on the board. with the Application Console panel displaying the application messages.

Sample Application Options

The Makefile included with the sample application allows the following parameters to be configured:

Parameter Possible Values Description
COMPILER GNU Use GCC compiler
^ ARMCC Use Arm Compiler 5
MEMORY ddr Use DDR memory
^ ocr Use On Chip RAM memory
SEMIHOSTED 1 Use debugger as console
^ 0 Use UART as console

In order to change a parameter, perform the following:
  • Clean the project
  • Edit the Makefile to change the parameter
  • Build the project

Cyclone V Bare Metal Example Using SoC EDS Standard Edition

Build U-Boot

Note: U-Boot can only be built on Linux.

1. Start an Embedded Command Shell 

~/intelFPGA/20.1/embedded/embedded_command_shell.sh

2. Build U-Boot 

# Convert handoff data to source code
cd $SOCEDS_DEST_ROOT/examples/hardware/cv_soc_devkit_ghrd
rm -rf software/bootloader
mkdir -p software/bootloader
bsp-create-settings \
	--type spl \
	--bsp-dir software/bootloader \
	--preloader-settings-dir "hps_isw_handoff/soc_system_hps_0" \
	--settings software/bootloader/settings.bsp

# Get the U-Boot source code
cd software/bootloader
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
git checkout -b test -t origin/socfpga_v2020.04

# Run the qts_filter to take the sources from the handoff 
# folder and the ones generated by bsp-create-settings, 
# format them appropriately and copy them to the U-Boot source code
./arch/arm/mach-socfpga/qts-filter.sh cyclone5 ../../../ ../ ./board/altera/cyclone5-socdk/qts/

# Build U-Boot
export CROSS_COMPILE=arm-eabi-
make socfpga_cyclone5_defconfig
make -j 24

The following files are created in $SOCEDS_DEST_ROOT/examples/hardware/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga:
  • spl/u-boot-spl - SPL executable
  • u-boot - U-Boot executable
  • u-boot-with-spl.sfp - Bootable file: four copies of SPL and one copy on U-Boot image

3. Create SPL debug script 

cat <<EOT > $SOCEDS_DEST_ROOT/examples/hardware/cv_soc_devkit_ghrd/software/bootloader/debug-spl.ds
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
tbreak spl_boot_device
continue
wait 60s

EOT

4. Create U-Boot debug script 

cat <<EOT > $SOCEDS_DEST_ROOT/examples/hardware/cv_soc_devkit_ghrd/software/bootloader/debug-u-boot.ds
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off
loadfile \$sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore \$sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
tbreak spl_boot_device
continue
wait 60s
delete
loadfile \$sdir/u-boot-socfpga/u-boot
start 
wait
restore \$sdir/u-boot-socfpga/u-boot.dtb binary &_end
tbreak relocate_code
cont
wait 60s
symbol-file "\$sdir/u-boot-socfpga/u-boot" ((gd_t*)\$r9)->reloc_off
thbreak board_init_r
cont
wait 60s

EOT

Run U-Boot SPL from Debugger

U-Boot SPL needs to be run, in order to initialize the hardware based on the HPS settings in the Quartus project, and also bring up DDR. FPGA needs to be configured before this step.

1. Start an Embedded Command Shell 

~/intelFPGA/20.1/embedded/embedded_command_shell.sh

2. Start a DS shell configured for Arm Compiler 5 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 5" bash

3. Start Arm DS IDE (Eclipse) 

armds_ide -data ~/ds.workspace&

4. In Eclipse Go to Run > Debug Configurations to open the Debug Configurations window

5. In the Debug Configurations window, select Generic Arm C/C++ Application, right click it and select New to create a new debug configuration

6. Rename the new configuration from “New_configuration” to “CV SPL”

7. In Connection Tab:
  • Select target to be Intel SoC FPGA > Cyclone V SoC (Single Core) > Bare Metal Debug > Debug Cortex-A9_0
  • Select target connection to be USB-Blaster
  • Click Browse under Bare Metal Debug Connection and select the USB Blaster instance

8. In Debugger Tab:
  • Select Run control to be Connect Only
  • Check Run debug initialization debugger script, and click the File System icon near it to browse for the script ~/intelFPGA/20.1/embedded/examples/hardware/cv_soc_devkit_ghrd/software/bootloader/debug-spl.ds
  • Click Debug button

9. Serial console will display that SPL ran fine and calibrated DDR successfully:

10. DS debugger will show SPL stopped on the spl_boot_device function

11. Exit the debugging section by pressing the red Disconnect from Target button

Exercise Sample Application

1. Start an Embedded Command Shell 

~/intelFPGA/20.1/embedded/embedded_command_shell.sh

2. Start a DS shell configured for Arm Compiler 5 

/opt/arm/developmentstudio-2020.1/bin/suite_exec -t "Arm Compiler 5" bash

3. Start Arm DS IDE (Eclipse) 

armds_ide -data ~/ds.workspace&

4. In Eclipse go to File > Import > General > Existing Projects into Workspace and click Next

5. Check Select archive file then click Browse and go to ~/intelFPGA/20.1/embedded/examples/software/Altera-SoCFPGA-HardwareLib-Timer-CV-GNU.tar.gz and click OK

6. Click Finish in the Import window.

7. The project is now imported.

8. Go to Project > Build to build the project

9. Go to Debug > Debug Configurations to open the Debug Configurations window.

10. In the Debug Configurations window, select the Altera-SoCFPGA-HardwareLib-Timer-CV-GNU-Debug configuration.

11. In the Debug Configurations window, Connection tab, click on the Browse button to select your USB Blaster instance.

12. In the Debug Configurations window, Debugger panel, check Execute debugger commands and enter the commands shown below - they will ensure that the debugger stops at the main function. Click Debug to start a debug session.

13. Application will be downloaded to the board, and ran up to the main function. Click on the green Continue button, or press F8 to let the application run.

14. The application will run to completion, toggling LEDs on the board. with the Application Console panel displaying the application messages.

Sample Application Options

The Makefile included with the sample application allows the following parameters to be configured:

Parameter Possible Values Description
COMPILER GNU Use GCC compiler
^ ARMCC Use Arm Compiler 5
MEMORY ddr Use DDR memory
^ ocr Use On Chip RAM memory
SEMIHOSTED 1 Use debugger as console
^ 0 Use UART as console

In order to change a parameter, perform the following:
  • Clean the project
  • Edit the Makefile to change the parameter
  • Build the project

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