The Altera SoC FPGA is a combination of a traditional system-on-a-chip (SoC) with a field programmable gate array (FPGA) in a single die fabricated on a 28nm process technology. The system-on-a-chip portion of the device is called the hard processor system (HPS) and it is tightly integrated into the FPGA fabric through a series of high performance memory mapped connections. These high performance paths between the HPS and FPGA fabric provide over 100GB/s bandwidth allowing you to extend your system functionality to include any following in a customizable single chip solution:

• Hardware accelerator
• I/O expansion
• Line-rate signal processing
• Protocol future-proofing
• Reconfigurable computing

At the heart of the Altera SoC FPGA device is the HPS, a complete embedded solution implemented as a hard silicon block. Instead of consuming numerous FPGA resources the HPS block provides a high performance embedded system in a small power envelope compared to a comparable system implements solely out of FPGA resources. This leaves more FPGA real-estate available for you to implement custom logic function to customize the Altera SoC FPGA to fit the needs of your end product. The HPS consists of the following system IP:

• ARM Cortex-A9 dual core microprocessor
• 512KB Level-2 cache
• 64kB on-chip RAM and up to 4GB of DDR2, DDR3, and LPDDR2 SDRAM
• QSPI, NAND, and SD/MMC non-volatile storage controllers
• (2x) USB 2.0 OTG, (2x) 10/100/1000Mbps EMAC
• (2x) SPI master, (2x) SPI slave, (2x) CAN, (2x) UART, (4x) I2C, 85-bit GPIO
• (5x) MPU timers, (6x) system timers

Want more information? See CycloneV Technical Reference Manual

-- YvesVandervennet - 18 Oct 2012