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Terasic DE1-SoC Development and Education Board
Terasic DE1-SoC Development and Education Board
01 August 2016 - 08:28
|
Version
24
|
Michael Daum
|
DE1-SoC
,
terasic
overview
features
resources
videos
Show All
DE1-SoC Board
Layout
Block Diagram
Board Features
The following hardware is provided on the board:
FPGA Device
Cyclone V
SoC
5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers
Configuration and Debug
Quad Serial Configuration device – EPCQ256 on FPGA
On-Board USB Blaster II (Normal type B USB connector)
Memory Device
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS
Communication
Two Port USB 2.0 Host (ULPI interface with USB type A connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver
Connectors
Two 40-pin Expansion Headers
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one
I2C
and one GPIO interface )
Display
24-bit VGA DAC
Audio
24-bit CODEC, Line-in, line-out, and microphone-in jacks
Video Input
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
ADC
Fast throughput rate: 1 MSPS
Channel number: 8
Resolution: 12 bits
Analog input range : 0 ~ 2.5 V or 0 ~ 5V as selected via the RANGE bit in the control registe
Switches, Buttons and Indicators
4 User Keys (FPGA x4)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
Six 7-segment displays
Sensors
G-Sensor on HPS
Power
12V DC input
Resources
Linux BSP (Board Support Package)
CD-ROM
Documents
Demo (DE1-SoC)
*if the film is unavailable, please kindly try another link below:
http://www.youtube.com/watch?v=aPXMkTJxD_s
Demo (DE1-SoC + MTL)
*if the film is unavailable, please kindly try another link below:
http://www.youtube.com/watch?v=xBLu_4tuVR4
DE1-SoC Board
Layout
Block Diagram
Board Features
The following hardware is provided on the board:
FPGA Device
Cyclone V
SoC
5CSEMA5F31C6 Device
Dual-core ARM Cortex-A9 (HPS)
85K Programmable Logic Elements
4,450 Kbits embedded memory
6 Fractional PLLs
2 Hard Memory Controllers
Configuration and Debug
Quad Serial Configuration device – EPCQ256 on FPGA
On-Board USB Blaster II (Normal type B USB connector)
Memory Device
64MB (32Mx16) SDRAM on FPGA
1GB (2x256Mx16) DDR3 SDRAM on HPS
Micro SD Card Socket on HPS
Communication
Two Port USB 2.0 Host (ULPI interface with USB type A connector)
USB to UART (micro USB type B connector)
10/100/1000 Ethernet
PS/2 mouse/keyboard
IR Emitter/Receiver
Connectors
Two 40-pin Expansion Headers
One 10-pin ADC Input Header
One LTC connector (One Serial Peripheral Interface (SPI) Master ,one
I2C
and one GPIO interface )
Display
24-bit VGA DAC
Audio
24-bit CODEC, Line-in, line-out, and microphone-in jacks
Video Input
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
ADC
Fast throughput rate: 1 MSPS
Channel number: 8
Resolution: 12 bits
Analog input range : 0 ~ 2.5 V or 0 ~ 5V as selected via the RANGE bit in the control registe
Switches, Buttons and Indicators
4 User Keys (FPGA x4)
10 User switches (FPGA x10)
11 User LEDs (FPGA x10 ; HPS x 1)
2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)
Six 7-segment displays
Sensors
G-Sensor on HPS
Power
12V DC input
Resources
Linux BSP (Board Support Package)
CD-ROM
Documents
Demo (DE1-SoC)
*if the film is unavailable, please kindly try another link below:
http://www.youtube.com/watch?v=aPXMkTJxD_s
Demo (DE1-SoC + MTL)
*if the film is unavailable, please kindly try another link below:
http://www.youtube.com/watch?v=xBLu_4tuVR4
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