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Advice on how to create a devicetree for SoC FPGA linux environments.
Recent Changes
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Table of Contents
Introduction
Early IO release is a feature where user can enable DDR functioning prior programming the core raw binary file (RBF) for speeding up the boot time. In this flow, the shared I/O and hard memory controller I/O are configured and released allowing HPS immediate access to them. This also enables availability of shared IO where core RBF can be obtained from TFTP server instead of flash. Afterward, the FPGA fabric is configured and released allowing HPS to access. It also played critical role and providing early response on time critical system.Feature Description
The RBF data can be programmed by issuing the fpga loadfs command with correct RBF type such as “periph”, “core”, and “combined” parameter, U-boot would do the rest of FPGA programming by feeding the RBF data from the flash to configuration subsystem (CSS) in FPGA portion of device, which is responsible to configure the FPGA fabric, as well as the I/O configuration and status registers (IOCSRs). Shared I/O, hard memory controller I/O, hard memory controller settings such as memory type, frequency and timings can be programmed by peripheral RBF. Configuring the FPGA fabric, FPGA I/O and FPGA PLL settings can be done through feeding CSS with core RBF. Both FPGA fabric and IOCSRs can also be configured one off by combining the both peripheral RBF and core RBF, which is called combined type RBF.Early I/O Release Design and Flow
SDMMC Booting Flow
SDMMC Booting Flow with Early I/O Release Enabled
SDMMC Booting Flow with Early I/O Release Disabled
DTS Design for SDMMC Booting with Early I/O Release Enabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-file = " ghrd_10as066n2.periph.rbf"; /*Bootloader setting: periph.rbf_filename */
early-release-fpga-config; /* set 'early-release-fpga-config' to true' */
};
……..
………
DTS Design for SDMMC Booting with Early I/O Release Disabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-file = " ghrd_10as066n2.rbf"; /*Bootloader setting: combined.rbf_filename */
};
……..
………
QSPI Booting Flow
QSPI Booting Flow with Early I/O Release Enabled
QSPI Booting Flow with Early I/O Release Disabled
DTS Design for QSPI Booting with Early I/O Release Enabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-offset = <0x00720000>; /*Bootloader setting: periph.rbf_ */
early-release-fpga-config; /* set 'early-release-fpga-config' to true' */
};
……..
………
DTS Design for QSPI Booting with Early I/O Release Disabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-offset = <0x00720000>; /*Bootloader setting: combined.rbf_ */
};
……..
………
NAND Booting Flow
NAND Booting Flow with Early I/O Release Enabled
NAND Booting Flow with Early I/O Release Disabled
DTS Design for NAND Booting with Early I/O Release Enabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-offset = <0x00720000>; /*Bootloader setting: periph.rbf_ */
early-release-fpga-config; /* set 'early-release-fpga-config' to true' */
};
……..
………
DTS Design for NAND Booting with Early I/O Release Disabled
/dts-v1/;
/*
* Bootloader: uboot
* Version: 1.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */
chosen {
cff-offset = <0x00720000>; /*Bootloader setting: combined.rbf_ */
};
……..
………
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