Getting Started

Golden System Reference Designs

Starting with the Quartus Prime 20.1, the GSRDs are documented on the following pages:

• Cyclone V SoC GSRD
• Arria 10 SoC GSRD
• Stratix 10 SoC L-Tile GSRD (23.4)
• Stratix 10 SoC H-Tile GSRD (23.4)
• GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile) (23.4)
• GSRD for Agilex 7 F-Series FPGA DevKit (2x F-Tile) (23.4)
• GSRD for Agilex 7 I-Series Transceiver-SoC DevKit (4x F-Tile) (23.4)
• GSRD for Agilex 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile) (23.4) (new)

Starting with GSRD 21.3, a single boot image approach is used, more details presented in Single Image Boot.

For pre 20.1 GSRDs, refer to Legacy Getting Started.

Bootloaders

• Building Bootloader for Cyclone V and Arria 10
• Building Bootloader for Stratix10 (23.4)
• Building Bootloader for Agilex 7 (23.4)

Configuring FPGA Fabric from Linux

• Agilex 7 Configuring FPGA Fabric From Linux
• Stratix10 Configuring FPGA Fabric From Linux

eMMC Boot

• Stratix 10 SoC with eMMC Storage on HPS
• Agilex 7 SoC With eMMC Storage On HPS

General Information

• Intel FPGA HPS Embedded Software Release Notes
• Intel® Simics® Simulator for Intel FPGAs Release Notes
• Git Introduction
• HOWTO Create a Device Tree

Remote System Update

• Agilex 7 SoC HPS Remote System Update
• Stratix 10 HPS Remote System Update
• Stratix10 RSU: Using Separate SSBL Per Bitstream
• Agilex 7 RSU: Using Separate SSBL Per Bitstream
• Remote System Update Compatibility

PCIe

• Cyclone V PCIe Root Port
• Arria 10 PCIe Root Port
• Arria 10, Cyclone V, Arria V PCIe Root Port
• Stratix 10 PCIe Root Port

Ethernet

• Cyclone V SoC Triple Speed Ethernet
• Arria 10 SoC Triple Speed Ethernet
• Cyclone V SoC RGMII
• Arria 10 SGMII
• Stratix 10 SGMII
• Agilex 7 SoC E-Tile 25Gbe IEEE1588 PTP
• Stratix 10 SoC 10Gbe IEEE1588 PTP

Debugging

• Remote FPGA Debug for Stratix 10
• Remote FPGA Debug for Agilex 7
• Linux Kernel Debugging With DS-5
• Linux Application Debugging With DS5
• Arm Development Studio Examples

Other Projects

• Intel Agilex 7 SoC Secure Boot Demo Design (FPGA First)
• Intel Agilex 7 SoC Secure Boot Demo Design (HPS First)
• Application Development with Yocto eSDK
• Setting up and Using Bridges on Agilex 7 SoC
• Enabling new QSPI parts in U-Boot and Linux