This is a AAEON board which uses Cyclone 10 GX FPGA with Intel processor. It is connected through PCIe Gen 2 by 4 lane. The setup uses UP CORE PLUS (http://www.up-board.org/ai-edge/up-core-plus/) and UP AI PLUS (http://www.up-board.org/ai-edge/ai-plus/) board.

Requirement

For the board setup to run with OpenCL, below is the requirement.

1. Download Intel FPGA SDK OpenCL Pro Edition v18.0
2. Ubuntu OS
3. Basler Camera (daA2500_14bc)

Compilation Setup

For FPGA bitstream Compilation. I would suggest you to compile the Cyclone 10 GX FPGA design using normal PC as UP CORE PLUS does not have the require specification to performed the compilation.

1. Unzip the up_aiplus.zip file in the attachment into "intelFPGA_pro/18.0/hld/board/" folder
2. Download
a. PipeCNN example design from github (https://github.com/doonny/PipeCNN)
b. Basler example design
3. Performed OpenCL compilation with the up_aiplus BSP.
a. "-board=up_aiplus" for normal UP Core Plus and UP AI Plus board design.
b. "-board=up_aiplus_basler" for design that include Basler CMOS Sensor interface

PipeCNN Demo

Below is the setup step for the demo design.

1. Install Intel FPGA RTE OpenCL Pro Edition v18.0
2. Unzip the up_aiplus.zip file in the attachment into "/home/upsquared/intelFPGA_pro/18.0/hld/board/" folder
3. Download the design from github into the "/home/upsquared/" folder
4. Download aocl.sh and library_path.sh into "/home/upsquared/" folder.
5. Download the conv.aocx into "/home/upsquared/PipeCNN/project" folder.
6. Program the FPGA through Quartus Programmer with the PipeCNN.jic file in the attachment.
7. Replace the makefile in "/home/upsquared/PipeCNN/project" folder with the Makefile in the attachment.
8. Download LSVRC 2012 Validation Set from http://academictorrents.com/details/5d6d0df7ed81efd49ca99ea4737e0ae5e3a5f2e5 and unzip into the UP CORE PLUS
8. Modify the main.cpp file in the "/home/upsquared/PipeCNN/project/host" folder on line 78 with the the correct Imagenet LSVRC 2012 Validation location.
9. Performed the instruction "make" in "/home/upsquared/PipeCNN/project" folder
10. Power down and power up the board before running the demo.

Running the demo.

1. Performed the instruction "source ./aocl.sh" and "./library_path.sh"
2. Performed the instruction "modprobe -r altera_cvp". This is needed if the altera_cvp in pre-installed with the OS.
3. Performed the instruction "aocl install"
4. Performed the instruction "aocl diagnose" to detect the OpenCL kernel is ready and "aocl diagnose acl0" to check the memory read write performance.
5. Go to "/home/upsquared/PipeCNN/project" folder and execute command "./run.exe conv.aocx"

Basler CMOS Sensor demo

Attach is 2 openCL kernel code. Basler_pipeline.cl is just performing direct output to CPU without any processing. Basler_sobel is performing sobel filtering (edge detection) in FPGA before passing the data back to CPU.

Below is the setup for compilation

1. Install Intel FPGA OpenCL Pro Edition v18.0
2. Unzip the up_aiplus.zip file in the attachment into OpenCL installation folder under board.
3. Setup the OpenCL environment.
4. Performed instruction "aoc basler_pipeline.cl -o bin/io_channel.aocx -board=up_aiplus_basler -v" or "aoc basler_sobel.cl -o bin/io_channel.aocx -board=up_aiplus_basler -v"

Below is the setup step for the sobel demo design.

1. Install Intel FPGA RTE OpenCL Pro Edition v18.0
2. Unzip the up_aiplus.zip file in the attachment into "/home/upsquared/intelFPGA_pro/18.0/hld/board/" folder
3. Unzip the apps.zip file in the attachment into "/home/upsquared/" folder
4. Download aocl.sh and library_path.sh into "/home/upsquared/" folder.
5. Program the FPGA through Quartus Programmer with the sobel.jic file in the attachment.
6. Performed the instruction "make" in "/home/upsquared/apps/io-channel" folder
7. Power down and power up the board before running the demo.

Running the demo.

1. Performed the instruction "source ./aocl.sh" and "./library_path.sh"
2. Performed the instruction "modprobe -r altera_cvp". This is needed if the altera_cvp in pre-installed with the OS.
3. Performed the instruction "aocl install"
4. Performed the instruction "aocl diagnose" to detect the OpenCL kernel is ready and "aocl diagnose acl0" to check the memory read write performance.
5. Performed the instruction "/home/upsquared/intelFPGA_pro/18.0/hld/board/up_aiplus/linux64/libexe/cmos_init" which set the Basler CMOS Sensor setting to initialize and start capturing image.
6. Go to "/home/upsquared/apps/io-channel" folder and execute command "./bin/host"