Altera SoC Triple Speed Ethernet Design Example
This design example demonstrates how to use Cyclone V SoC with Triple Speed Ethernet (TSE) example design release packages.

Board: Altera Cyclone V SoC Board
Tools Version: 14.0
State: running
Members: LuisLui


This design example demonstrates how to use Cyclone V SoC with Triple Speed Ethernet (TSE) example design release packages. It leverage on Altera Ethernet soft IP implemented in FPGA and used Modular Scatter-Gather Direct Memory Access (mSGDMA) IP for data transfer within the system.

The purpose of this design example is to serve as a starting point for TSE system designs with SoC. It consists of both hardware designs and software packages. It adopts CV SoC Development Board as hardware platform to implement TSE with SoC subsystem design. Due to the features of CV SoC Development Board only consist of 10/100 Ethernet PHY connected to FPGA pins, TSE soft IP in this design example will only be able to operate in 10Mbit and 100Mbit modes.

Release Contents

The Altera SoC TSE Design Example sources and prebuilt binaries can be downloaded from this link.
Folder File Description
bin linux-socfpga-tse-14.0-cv-bin.tar.gz

Cyclone V binaries archive

All the prebuilt images needed for demo and building the SD Image sd_image.bin is a 2GB

SD card image file contains all the require components for demo, including Preloader, U-boot, rootfs, kernel image and device tree blob

hw cv_soc_tse_ed.tar.gz Hardware design example zip file, consist of necessary system file to generate sof image
src ed-tse-yocto.patch Patch to Yocto component - poky-socfpga
boot.script U-boot script

Quick Start Guide

  1. Board setup is based on Altera GHRD Getting Started Guides.
  2. Prepare SD card by following the GSRD - Booting Linux Using Prebuild SD Card Image, untar linux-socfpga-tse-14.0-cv-bin.tar.gz and program sd_image.bin into SD card.
  3. Slot in the SD card, insert Ethernet cable to ENET1/ENET2 before warm reset HPS to load SD card image.
  4. U-boot will load FPGA RBF image file from SD card to FPGA.
  5. Kernel will auto bring up the eth1 and eth2 during booting time and run DHCP to obtain IP address.
  6. Wait until booting process is done, login as root at kernel terminal.
  • Interface eth1 in Linux is referred to J34 (ENET1) port and eth2 is referred to J33 (ENET2) port.
board setup.png


Hardware requirement

  • Cyclone V SoCDevelopment Kit
    • Rev C - fully compatible
    • Rev D - required R522 pull down resistor to be removed, refer here for more rework info
  • RJ45 Ethernet cable
  • 4GB microSDHC flash card
  • SD card with sd_image.bin

Software requirement

This design example is build based on Cyclone V GSRD (Golden System design example) and tested with Quartus II version 14.0. It is recommended for user to go through below material before get started with this design example.
  • Please refer this link for Cyclone V SoC Development Kit documentation and installation files.
  • Please refer to GSRD User Manualand perform the following action:
    • Step through “Prerequisites”, “GHRD Overview” and “Getting Started Guide”
    • Understand the “Development Flow Overview”

Hardware Architecture Overview

block diagram 2.png

Qsys Top Level:
  • Hard Processor System (HPS)
  • TSE Sub Block 0
  • TSE Sub Block 1
  • Interrupt Capture Module
  • System ID Peripherals
TSE Sub Block:
  • TSE
  • Tx mSGDMA
  • Rx mSGDMA
  • Only one MDIO bus is exposed for accessing PHY registers due to CV SoC development board feature in a single chip of dual channel Mii PHY.
  • This design example is using TSE Sub Block 0 MDIO module connects to FPGA IO to access to PHY register.
  • Only the first TSE MAC instance will has its MDIO module enable, but not for the second TSE MAC instance.
  • Software will manipulate the second PHY register via the first TSE MAC MDIO space.
As a host processor in system, the HPS has access to all the peripherals in FPGA, including TSE MAC, System ID, and mSGDMA via the AXI Bridges of HPS. Take note that only AXI Bridges are AXI Interfaces while other peripherals are based on Avalon MM Interfaces. The AXI to Avalon MM conversion is handled by Qsys fabric.

TSE Parameters Configuration

*Take note that Linux driver is design to support Modular SGDMA. It is recommended for user to migrate from SGDMA to modular SGDMA to be fully compatible with software driver.

Below diagram illustrates the configuration of TSE IP in accordance to Linux driver features:

  • The Linux driver only supports TSE Core Variation “10/100/1000Mb Ethernet MAC”
  • The Linux driver only supports MII/GMII interface
  • *Take note that 1G speed is not tested due to hardware limitation
  • The Linux driver requires “Include Statistics Support” and “Enable 64-bit statistics byte counters” to be checked in the TSE’s “MAC Options” configuration tab to supports design with full 64-bit statistics enabled
  • The Linux driver requires “Include Multicast hashtable” hto be checked in the TSE’s “MAC Options” configuration tab.
  • The Linux driver requires “Align packet headers to 32-bit boundary” to be checked in the TSE’s “MAC Options” configuration tab.
  • The Linux driver requires “Enable VLAN detection” to be enabled
  • MDIO module is only enabled on TSE Sub Block 0
  • Clock divisor for MDIO is calculated based on TSE User Guide, for more information, please refer to TSE User Guide page 3-3.
  • SGMII support is not currently available, “PCS/Transceiver Options” page are remain as default.

Modular SGDMA Parameters Configuration

Ttransmit and receive mSGDMA consist of different direction path. Memory-Mapped-Streaming mSGDMA is used for transmit path FIFO, while Strearming-to-Memory-Mapped mSGDMA is used for receive path FIFO.

Following diagram shows the configuration for both mSGDMA:




  • “Unaligned access” feature must be enabled for forwards/backwards compatibility for both mSGDMA
  • The Linux driver does not currently support Scatter/Gather packet transmit and receive since the benefit of Scatter/Gather is limited by the TSE’s lack of Checksum Offload support”.

Memory Map

Refer to soc_tse_ed_5csxfc6.html in qsys folder.

*Take note that soc_tse_ed_5csxfc6.html is not in the project directory by default. User need to run Qsys generation in order to generate this file.

Quartus II Design Files

Below is some of the important file in this design example:
soc_tse_ed_5csxfc6.qsys Top lovel Qsys system block
sub_tse_w_dma.qsys TSE Qsys system block
sub_tse_w_dma_no_mdio.qsys TSE Qsys system block without exporting MDIO conduits
soc_tse_ed_top.v Top level RTL
soc_system_timing.sdc Timing constraint file

Software Development Flow

Yocto Flow

The complete Yocto software flow is similar to GSRD flow. However, Yocto patch needs to be applied before build binaries. This section describes the additional flow require to build binaries.

Setting Up Yocto Environment

Please follow this link to setup Yocto environment before starting this section.

Apply Yocto Recipes and Patch for TSE design example

Use below command to acquire poky source from Rocketboards Git:
$ git clone
$ cd poky-socfpga
$ git checkout -b tse-ed ACDS14.0_REL_GSRD_PR

Download the patch from release content section, apply the patch with below command:
$ git am ed-tse-yocto.patch

Build U-Boot/Kernel/Rootfs:
$ source altera-init
$ bitbake virtual/bootloader $ bitbake virtual/kernel $ bitbake altera-tse-image

Output files:
u-boot-socfpga_cyclone5.img U-Boot image
zImage Compressed kernel image
altera-tse-image-socfpga_cyclone5.ext3 Root Filesystem as ext3 image
altera-tse-image-socfpga_cyclone5.tar.gz Root Filesystem in tar gzip archive format

Generate Device Tree Blob

Use below command to generate device tree blob:
$ sopc2dts --input <tse_design>.sopcinfo --output socfpga.dtb –type dtb --board <tse_design>_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks

  • *.sopcinfo and *.xml files is store at TSE example design hardware directory.
Output file: socfpga.dtb

For more details about device tree generation, please refer to GSRD User Manual - Generating the Device Tree.

Generate Preloader

For more details about preloader generation, please refer to GSRD - Generating and Compiling the Preloader.

Output file: preloader-mkpimage_cyclone5.bin

Convert FPGA SOF to RBF

For more details about converting FPGA image from .sof to .rbf, please refer to GSRD - Compile Hardware Design.

Output file: <tse_design>.rbf

Build SD Card Image

Replace all required component into SD Card, or build and replace the whole image.

For more details about SD card image generation, please refer to GSRD - Creating and Updating SD Card.


Please refer to this link for Ethernet design example demo testing.

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