Demo

The boot flow will be similar to the GSRD. Upon boot, the default hardware persona will be booted. The default persona has a System ID in place. This System ID can be read by the kernel. For partial reconfiguration there are multiple DTB and DTBO compared to a system without partial reconfiguration, which only needs one DTB. The base DTB is applied on boot and it is loaded by the bootloader. The DTB consists of the FPGA region (all non-PR IP in the FPGA) and have a node for the FPGA PR region. The DTBO for the PR region describes the device tree entries in the PR region only.

In this demo, there are two hardware personas, both with a different System ID. The DTSO fragments for each PR freeze region will be generated along with the base DTS. These device tree information are consumed by the kernel for dynamic device tree update to the kernel device tree overlay.

The freeze logic and FPGA manager drivers are responsible for partial reconfiguration. The freeze logic driver issues the freeze command to freeze all communication in the PR region. The freeze logic IP freezes the AVMM bridge according to the AVMM specification and the connected signals ­­as specified by the IP.

With the PR region freeze, the device tree overlay driver in kernel is used to update the dtso fragment. This is important as the memory map in the PR region may change and the kernel now have an updated information about the actual hardware after the PR completed by updating the device tree overlay. The FPGA manager driver will be used to configure the new persona RBF bitstream and this reconfigures the PR region. With the new RBF of the PR and dtso updated, the freeze logic driver then will give the instruction to unfreeze the PR region. The software modules that is available in the PR region will then be loaded. This completed the partial reconfiguration.

Access overlays using dtbt

Check the default static overlay region:

root@arria10:~# dtbt -l
1 fpga_static_region.dtbo applied /sys/kernel/config/device-tree/overlays/1-fpga_static_region.dtbo

Apply persona 0 overlay:

root@arria10:~# dtbt -a persona0.dtbo -p /boot
Set dtbo search path to /boot
Applying dtbo: persona0.dtbo
[ 78.934742] fpga_manager fpga0: writing persona0.rbf to SoCFPGA Arria10 FPGA Manager

Check the System ID value for the default persona 0:

id t@arria10:~# cat /sys/bus/platform/drivers/altera_sysid/ff200800.sysid/sysid/id
3405707982

This is the System ID value placed in pr_region.qsys.

Remove the persona 0 overlay:

root@arria10:~# dtbt -r persona0.dtbo -p /boot
Set dtbo search path to /boot
Removing dtbo: 2-persona0.dtbo

Apply persona 1 overlay:

root@arria10:~# dtbt -a persona1.dtbo -p /boot
Set dtbo search path to /boot
Applying dtbo: persona1.dtbo
[ 437.905424] fpga_manager fpga0: writing persona1.rbf to SoCFPGA Arria10 FPGA Manager

Check the System ID value for persona 1:

id t@arria10:~# cat /sys/bus/platform/drivers/altera_sysid/ff200900.sysid/sysid/
4207856382

This is the System ID value placed in pr_region_persona.qsys.

Remove the persona 1 overlay:

root@arria10:~# dtbt -r persona1.dtbo -p /boot
Set dtbo search path to /boot
Removing dtbo: 2-persona1.dtbo

References

Arria 10 SoC Hardware Reference Design That Demonstrates Partial Reconfiguration