Introduction

Altera Cyclone V SoC has 2 Ethernet Media Access Controller (EMAC) peripherals embedded along with the A9 core in the Hard Processor System (HPS). Each EMAC can be used to transmit and receive data at 10/100/1000 Mbps over Ethernet connections in compliance with the IEEE 802.3 specification.

In a huge system design which utilizes a lot of the HPS peripheral components, users will very likely run into a situation where only 1 of the EMAC output can be channeled to the HPS dedicated IOs. This limitation can be a great hindrance to complex design which needs multiple Ethernet interfaces to meet the design requirement.

The advantage brought by the RGMII standard along with the ability to implement a multiport Ethernet PHY design on the FPGA becomes the motivation to develop an example design which utilizes the HPS MAC.

Release Contents

The Altera Cyclone V SoC RGMII Design Example sources and prebuilt binaries can be downloaded from this link.

Folder	File	Description
bin	linux-socfpga-rgmii-cv-bin.tar.gz	Cyclone V binaries archive All the prebuilt images needed for demo and building the SD Image sd_image.bin is a 2GB SD card image file contains all the require components for demo, including Preloader, U-boot, rootfs, kernel image and device tree blob
hw	cv_soc_rgmii_ed.tar.gz	Hardware design example zip file, consist of necessary system file to generate sof image
src	boot.script	U-boot script

Prerequisites

The following hardware and software components are required to implement this design:

Hardware

• Cyclone V SoCDevelopmentKit
• RJ45 Ethernet cable
• 4GB microSDHC flash card
• HSMC Terasic Ethernet daughter card

*Take note that this design example require -7 speed grade device to close timing for RGMII external path delay

Software

This design example is build based on Cyclone V SoC GSRD (Golden System design example) and tested with Quartus II version 14.0.2. It is recommended for user to go through below material before get started with this design example.

• Quartus II version 14.0.2
• SoC Embedded Design Suite (SoCEDS) version 14.0.1
• Please refer this link for Cyclone V SoC Development Kit documentation and installation files.
• Please refer to GSRD User Manual and perform the following action:

Quick Start Guide

Setup Board

Board setup is based on Altera GHRD Getting Started Guides.

Obtain Image

Download and unzip the binary file from release contents.

$ cd ~
<Download linux-socfpga-rgmii-cv-bin.tar.gz>
$ tar xzf linux-socfpga-rgmii-cv-bin.tar.gz

Program SD card

Load sd_image.bin into sd card by following the below command.

$ cd ~/linux-socfpga-rgmii-cv-bin 
$ sudo dd if=bin/linux/sd_image.img of=/dev/sdx
* Please replace ‘dev/sdx’ with the name of the SD card device on your host computer.
$ sync

Boot

Plug the HSMC daughter card into slot.

Slot in the SD card, insert Ethernet cable to port eth0 and eth1 as shown in picture before warm reset HPS.

U-boot will load FPGA RBF image file from SD card to FPGA.

Wait until booting process is done, login as root at kernel terminal.

User needs to run "udhcpc -i eth0" command to obtain IP address for eth0 which is used for RGMII.

Hardware Implementation

The Ethernet RGMII example design consists of a HPS subsystem surrounded by the various IP residing in the FPGA fabric. The HPS is configured to enable UART, SDMMC Controller, 2 GMAC controllers and the H2F AXI Light Weight Bridge for communication with the FPGA domain.

On the FPGA side, there is an AXI to Avalon Bridge which will convert AXI protocol signals coming over from HPS to Avalon-MM compliant signals. The System ID block can be used to ensure that the clock signals are active.

Altera GMII to RGMII Adapter is not directly connected to HPS component. Instead an intermediate component called Altera HPS EMAC Interface Splitter core is used as a bridge between HPS core and Altera GMII to RGMII Adapter core. The intermediate component is responsible to split the EMAC conduit interface output from HPS core into several interfaces according to their function (hps_gmii, ptp, mdio interfaces). It also responsible to manage differences between EMAC interfaces of Arria V/Cyclone V HPS and Arria 10 HPS.

The GMII to RGMII adapter core provides a single to double data rate conversion of the data coming out from the EMAC0. The RGMII interface is connected to Ethernet port of HSMC connector. EMAC1 is connected to onboard Micrel PHY.

The MPU is running the Linux OS which will be responsible for proper register setting on the peripheral components which makes up the RGMII system design. A JTAG Master which resides on the FPGA will aid hardware debug activities as it can be used to send and receive configuration bits via the system console interface.

Memory Map

Quartus Design Files

Below is some of the important file in this design example:

cv_soc_rgmii_5csxfc6.qsys	Top lovel Qsys system block
cv_soc_rgmii_5csxfc6.v	Top level RTL
soc_system_timing.sdc	Timing constraint file

Important Note

There is timing model issue in Quartus 14.0.2. Basically timing arc for the first node of tx_clk driven register was missing from HPS timing model, and this node is important to ensure the first path between HPS and first FPGA register driven by tx_clk is analyzed. In order use the correct timing model from Quartus, below is workaround.

1. An INI file is required to enable the internal timing path from HPS clock mux.
2. Open and generate cv_soc_rgmii_5csxfc6.qsys file.
3. Remove all the content inside the file cv_soc_rgmii_5csxfc6/synthesis/submodules/cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces.sdc
4. Compile quartus

Altera HPS Emac Interface Splitter Core IP and Altera GMII to RGMII Adapter Core IP are hidden in Quartus 14.0.2. To enable these 2 hidden components, please perform the following steps:

1. In Quartus, go to Tools-→Options-→Internet Connectivity-→Talkback Options-→Check "Enable sending TalkBack data to Altera"
2. Launch Qsys, right click on empty area on left panel of IP Catalog. Click "Show Hidden Components"

Software Development Flow

Angstrom Flow

This design will built based on Angstrom instead of Yocto enviroment . Angstrom is a Linux distribution, targetting Embedded Systems. More information can be found on the Angstrom documentation.

How to get the build scripts

First, the repository with the angstrom build scripts must be cloned:

$ git clone http://git.rocketboards.org/angstrom-socfpga.git

Then, checkout the branch matching the tag version (ACDS14.0.1_REL_GSRD_PR):

$ cd angstrom-socfpga
$ git checkout -b rgmii-ed-socfpga ACDS14.0.1_REL_GSRD_PR

Setting Up Environment

# Configure the build environment for Cyclone5
$ MACHINE=socfpga_cyclone5 ./oebb.sh config socfpga_cyclone5
$ source enviroment-angstrom-v2013.12

Build U-Boot/Kernel/Rootfs

$ MACHINE=socfpga_cyclone5 bitbake virtual/bootloader
$ MACHINE=socfpga_cyclone5 bitbake linux-altera-ltsi
$ MACHINE=socfpga_cyclone5 bitbake extended-console-image

Output files

u-boot-socfpga_cyclone5.img	U-Boot image
zImage	Compressed kernel image
extended-console-image-socfpga_cyclone5.ext3	Root Filesystem as ext3 image
extended-console-image-socfpga_cyclone5.tar.gz	Root Filesystem in tar gzip archive format

Generate Device Tree Blob

EMAC Interface Splitter must be included as phandle in device tree (cv_soc_rgmii_5csxfc6_board_info.xml in the hardware design will add this for you).

hps_0_gmac0: ethernet@0xff700000 { compatible = "synopsys,dwmac-14.0", "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = < 0xFF700000 0x00002000 >; interrupt-parent = < &hps_0_arm_gic_0 >; interrupts = < 0 115 4 >; clocks = < &emac0_clk >; clock-names = "stmmaceth"; interrupt-names = "macirq"; mac-address = "[00 00 00 00 00 00]"; status = "okay"; address-bits = < 48 >; max-frame-size = < 3800 >; local-mac-address = [ 00 00 00 00 00 00 ]; phy-mode = "rgmii-id"; snps,phy-addr = < 0xFFFFFFFF >; phy-addr = < 0xFFFFFFFF >; altr,emac-splitter = < &hps_emac_interface_splitter_0 >; }; hps_emac_interface_splitter_0: splitter@0x100000000 { compatible = "altr,emac-splitter-1.0"; reg = < 0x00000001 0x00000000 0x00000008 >; clocks = < &clk_0 >; };

Use below command to generate device tree blob:

$ sopc2dts --input cv_soc_rgmii_5csxfc6.sopcinfo --output socfpga.dtb –type dtb --board cv_soc_rgmii_5csxfc6_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks

Note:

• *.sopcinfo and *.xml files is store at RGMII example design hardware directory.

Output file: socfpga.dtb

For more details about device tree generation, please refer to GSRD User Manual - Generating the Device Tree.

Generate Preloader

For more details about preloader generation, please refer to GSRD - Generating and Compiling the Preloader.

Output file: preloader-mkpimage_cyclone5.bin

Convert FPGA SOF to RBF

For more details about converting FPGA image from .sof to .rbf, please refer to GSRD - Compile Hardware Design.

Output file: <rgmii_design>.rbf

Build SD Card Image

Replace all required component into SD Card, or build and replace the whole image.

For more details about SD card image generation, please refer to GSRD - Creating and Updating SD Card.

Demo

Refer to this link for Ethernet Design Example Demo Testing.