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ECC Demo
Demo showing ECC on Altera SoC Development Board

27 June 2015 - 02:14 | Version 13 | | ECC, Preloader, U-boot, demo

Board: AlteraSoCDevelopmentBoard
Tools Version: 13.1
State: running
Members: Radu Bacrau

This demo project illustrates how the ECC for the external HPS DRAM controller is able to detect and correct single bit errors and also detect double bit errors.

Starting with ACDS and SoC EDS version 13.0sp1 the ECC is automatically enabled and working in the background correcting single bit errors and detecting double bit errors for all projects that have the HPS external DRAM memory in Qsys configured as ECC. Note that the ECC interrupt needs to be treated by upper layers of software if visibility into ECC events is desired.

This demo uses the ECC interrupt to provide U-boot with visibility and reporting of both corrected single bit errors and detected double bit errors.

Note that this is a demo, not an example design project. The demo is especially built to be able to always correctly execute even when uncorrectable double bit errors are encountered. Customers should not take or use the code as it’s not a normal use case.

For more details about ECC in the context SoC FPGA see the whitepaper at http://www.altera.com/literature/wp/wp-01179-ecc-embedded.pdf.

ECC Introduction

Increased hardware integration, ever reducing geometries and decreasing supply voltages make modern ICs more susceptible to various types of electromagnetic and particle radiation. While the increased capabilities bring huge rewards, more attention has to be paid to the probability of soft errors, especially in critical applications.

Soft errors happen when a memory bit cell is flipped due to impact from a charge foreign to the memory device. The source of the charge can be one of the following:
  • Low energy alpha particles emitted by the materials in the packaging materials
  • High energy alpha particles from cosmic rays
  • Gamma rays from natural background radiation or from cosmic rays

Earth's atmosphere is a significant shield for cosmic rays and particles, but it is not impenetrable. High energy alpha particles for example can pass through many meters of concrete. Packaging materials can be very well controlled for radioactive contamination, but they will never be perfectly pure. Also the effects of background radiation cannot be completely eliminated.

The problem is even more accentuated in aerospace applications, where the atmospheric shield has less impact, and the consequence of errors is more severe.

ECC (Error Correcting Code) is a mechanism that allows the memory controller to:
  • Detect and correct single bit errors
  • Detect double bit errors

ecc.png

ECC is implemented by making the memory wider and storing additional information for each memory word. On writes the ECC bits are computed and stored together with the requested data. On reads, the stored ECC bits are compared against the computed ECC bits. When they match, the data is returned without intervention. If there is a single bit error the controller will correct the data and pass it to the requester, raising an optional flag. The controller also has the option of writing back the corrected data in memory. If there is a double bit error the controller raises a flag to allow the system to gracefully respond to the event.

ECC on SoC FPGA

The ECC mechanism is implemented for the following SoC FPGA memories:
  • External DDRAM
  • On Chip RAM
  • L2 Cache
  • NAND Flash
  • Peripheral memories: EMAC, USB, SD, NAND Flash Controller, DDRAM Controller

Note that other mechanisms besides ECC are also used to protect the SoC FPGA from soft errors:
  • L1 Data and Instruction Caches are protected by Single Error Detection (SED) using Parity checks
  • FPGA configuration bits are protected by "scrubbing" - an industry standard of detecting and signaling errors

socfpga-ecc.png

ECC for External DRAM

External memory systems with 16- or 32-bit wide data lanes between the SoC FPGA and the external memory require six or seven additional storage bits of ECC, respectively. Altera’s architecture simplifies this by defining that one additional byte-wide memory be used for either scenario.

external-dram-ecc.png

ECC Demo

Starting with ACDS and SoC EDS version 13.0sp1 the ECC is automatically enabled by the Preloader for all projects that have the HPS external DRAM memory configured as ECC in Qsys. For such projects the ECC is working in the background, correcting single bit errors. Nothing additional needs to be done in order to have this feature.

The memory controller also has the ability to report the detected single bit errors and double bit errors to the HPS through an interrupt. This demo shows how this interrupt can be used to provide HPS visibility into the ECC events reported by the DRAM controller.

Overview

The demo is based on U-boot code and and is based on the standard Preloader → U-boot flow with the following modifications:
  • U-boot is run from FPGA DDRAM memory to allow errors on HPS DDRAM memory
  • Preloader zeroes out the HPS DDRAM memory, so that reads from HPS memory will not trigger detection of double bit errors
  • ECC interrupt is enabled in U-boot to allow signalling errors to user
  • U-boot has some additional scripts defined, to enable simple demo usage

ecc-demo.png

The method of introducing errors is by shorting two test pins on the Altera SoC Development Board. Because this method does not allow precise error injection, the application may become unstable when introducing double bit errors. This happens when instructions fetched from external DRAM become corrupted and the application cannot continue. In order to avoid this potential issue, the U-boot code is run from FPGA DDRAM memory.

The demo code is run as an U-boot script that performs the following:
  1. Fills buffer A at adress 0x100_0000 in HPS DRAM with 0xFFFFFFFF
  2. Slowly fills buffer B at address 0x200_0000 in HPS DRAM with 0xFFFFFFFF, while the user can introduce SBEs (Single Bit Errors) or DBEs (Double Bit Errors) by shorting test points on the board.
  3. Compares buffers A and B and displays whether the buffers were the same and the number of errors.

How to Introduce Errors

The Altera SoC Development board allows the user to introduce errors in the HPS DRAM by exposing the following two test points:
  • TP5 - DDR3_HPS_DQ14
  • TP6 - DDR3_HPS_DQ15

The user can introduce:
  • SBE (Single Bit Errors) by shorting either TP5 or TP6 to ground
  • DBE (Double Bit Errors) by shorting both TP5 and TP6 to ground simultaneously

introducing-errors.png

Running the ECC Demo

You will need the following in order to run the ECC demo:
  • Host PC running Linux or Windows
  • Altera SoC Development Board
  • Micro SD card (any capacity over 2MB will work)
  • Quartus II Programmer (or Quartus II software)

At a high level running the demo involves the following:
  1. Program FPGA with the provided SOF file
  2. Program SD card with the provided image file
  3. Boot board to U-boot prompt
  4. Run the ECC demo script
  5. Introduce errors

The detailed list of required steps is:

1. Download the attached SD card image from here: Compressed SD card image file containing ECC demo software and uncompress it to obtain the ecc_demo_sd_image.img file.

2. Write the SD card image to the micro SD card using either dd on Linux or Win32 Disk Imager on Windows.

See Linux Getting Started on Altera SoC Development Board - Using SD Card Image for instructions on how to use dd.

The Win32DiskImager can be obtained from this link: http://sourceforge.net/projects/win32diskimager/.

3. Download the compressed SOF file from this location: Compressed SOF file containing ECC demo hardware image and uncompress it to obtain the ecc_demo_hardware.sof file.

4. Power up board and configure the FPGA with the SOF file using the Quartus II Programmer

5. Insert micro SD card in slot and press HPS COLD reset button (S7) to boot HPS.

The SPL Preloader will be executed, and it will also zero out the HPS DRAM memory to initialize the ECC bits. Then U-boot will get executed. Press any key to stop the countdown.

This is how the console will look like: 

U-Boot SPL 2012.10-00012-g455c681 (Jun 26 2013 - 14:22:47)
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: ECC Enabled
SDRAM: Initialize ECC bits...done
DESIGNWARE SD/MMC: 0

U-Boot 2012.10-00012-g455c681 (Jun 26 2013 - 14:22:47)

CPU   : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone 5 Board
DRAM:  512 MiB
MMC:   DESIGNWARE SD/MMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
SDRAM: ECC Enabled
Net:   mii0
Warning: failed to set MAC address

Hit any key to stop autoboot:  3

6. Run the demo script 

# run ecc_demo

In case the user does not introduce any error, the output will look like this: 

Write buffer A: 640 words at address 0x100_0000

During writing to buffer B, please
- short single pad to ground for single bit error, or
- short both pads to ground for double bit error

Write buffer B: 640 words at address 0x200_0000
20%
40%
60%
80%
100%

Writing done. You can now stop introducing errors

Comparing buffer A with buffer B
Total of 640 word(s) were the same
All errors were corrected

Number of single bit error occurred is
sdram_ecc_sbe=0

In case the user introduces some SBEs the output will look similar to this: 

Write buffer A: 640 words at address 0x100_0000

During writing to buffer B, please
- short single pad to ground for single bit error, or
- short both pads to ground for double bit error

Write buffer B: 640 words at address 0x200_0000
20%
40%
60%
80%
100%

Writing done. You can now stop introducing errors

Comparing buffer A with buffer B
Info: SDRAM ECC SBE @ 0x00400028
Info: SDRAM ECC SBE @ 0x00400118
Total of 640 word(s) were the same
All errors were corrected

Number of single bit error occurred is
sdram_ecc_sbe=4

In case the user introduces also DBEs the output will look similar to this: 

Write buffer A: 640 words at address 0x100_0000

During writing to buffer B, please
- short single pad to ground for single bit error, or
- short both pads to ground for double bit error

Write buffer B: 640 words at address 0x200_0000
20%
40%
60%
80%
100%

Writing done. You can now stop introducing errors

Comparing buffer A with buffer B
Error: SDRAM ECC DBE occurred
sbecount = 4
erraddr = 00400068
dropcount = 00000000
dropaddr = 00000000
word at 0x01000340 (0xffffffff) != word at 0x02000340 (0xffff3fff)
Total of 208 word(s) were the same

Number of single bit error occurred is
sdram_ecc_sbe=0

Recompiling the Demo Code

The demo is already provided as a binary SD card image. This section shows how to get the source code, compile the demo and re-create the SD card.

In order to recompile the Demo code you will need the following:

The following steps are needed in order to recompile the demo:

1. Clone the U-boot git tree and checkout the proper version: 

$ cd ~
$ git clone http://git.rocketboards.org/u-boot-socfpga.git
$ cd u-boot-socfpga
$ git checkout -b <test_branch_name> origin/demo_sdram_ecc

Replace <test_branch_name> with the name of the branch you want to use locally.

2. Compile the SPL (Preloader) and U-boot 

$ ~/altera/13.0sp1/embedded/embedded_command_shell.sh
$ cd ~/u-boot-socfpga
$ export CROSS_COMPILE=arm-none-eabi-
$ make mrproper; make socfpga_cyclone5_config; make

3. Add the mkimage header required by BootROM on top of SPL Preloader binary 

$ ~/altera/13.0sp1/embedded/embedded_command_shell.sh
$ cd ~/u-boot-socfpga
$ mkpimage -o spl/u-boot-spl.img spl/u-boot-spl.bin spl/u-boot-spl.bin spl/u-boot-spl.bin spl/u-boot-spl.bin

4. Determine the device associated with the SD card on the host by running the following command before and after inserting the card in the reader: 

$ cat /proc/partitions

Let's assume it is /dev/sdx.

5. Format SD card

Wipe out the partitioning on the SD card: 

$ sudo dd if=/dev/zero of=/dev/sdx bs=1024 count=2048
$ sudo sync

Create a custom 1MB partition at offset 1MB with id=a2: 

$ sudo fdisk /dev/sdx
then type the following, pressing "Enter" after each line:
n 
p 
1
2048
+1024K
t
a2
w

6. Write SPL (Preloader) and U-boot binaries to the card 

$ sudo dd if=spl/u-boot-spl.img of=/dev/sdx1 bs=64k seek=0
$ sudo dd if=u-boot.img of=/dev/sdx1 bs=64k seek=4
$ sudo sync

7. If desired, you can re-create the SD card image 

$ sudo dd if=/dev/sdx of=ecc_demo_sd_image.img bs=1024 count=2048
$ gzip -9 ecc_demo_sd_image.img

Hardware Project

The Quartus II Project used to create the SOF file used to configure the FPGA for the demo can be downloaded from here: Compressed ECC demo hardware project.It is a simple project, that instantiates the following components:
  • HPS
  • SysId
  • FPGA DRAM

Attachments

References

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