State: running

Introduction

The network sub-system always plays as an important role in a typical embedded system. The HPS inside SoCFPGA normally just has two Ethernet ports as a hard IP. How to extend Ethernet connect ability to more ports, more various devices (PHY or Networking processor/Switch ASIC)? This design will satisfy this requirement by implementing an Ethernet switch IP inside SoCFPGA, connecting with HPS, NIOSii CPU and external Ethernet ports.

System Overview

fes.png

Once powered on, Nios run firstly. It will communicate with a externel host by Port2 and Port1. When Hps is ready, communication will happen between hps and a externel host by Port0 and Port1.

PS:FES is an Ethernet switch IP block designed to be used in programmable environments. FES includes multiple Ethernet Media Access Controller (MAC) functional entities and provides MII/GMII interfaces for Ethernet PHY devices and optionally for a host system CPU.

Specification

  • Implemented on Altera CycloneV SoC Board and Altera Arria 10 SoC Board.
  • DDR3 on hps side, shared with FPGA.
  • Hps runs Linux; Fpga runs Nios.

Kernel

  • kernel can deal with fixed-link package.
  • .CONFIG_FIXED_PHY=y.

Driver

flx_frs:Driver creates a Linux net device for each switch port. Net devices of the external ports are attached to PHY devices, if so configured. This allows existing Linux PHY drivers to be used for link mode monitoring in order to keep FES registers synchronized with current link mode.

flx_eth_mdio:mdio driver.

DeviceTree

Fes Devicetree.JPG

Result:

Fes Result.png

Give us your feedback

© 1999-2017 RocketBoards.org by the contributing authors. All material on this collaboration platform is the property of the contributing authors. Privacy.