Overview

The Sodia board implements the same audio IC (wm8731) as Terasic's DE1-SOC. In addition, the same interface can be applied to connections between SOCFPGA and wm8731. (As a difference, the connection of the control interface is limited to the HPS side [I2C1] in the case of Sodia)
So, this project corresponded in the same way as the preceding DE1-SoC ALSA audio project.
Especially, The driver software is completely diverted in a state of no modification. See Here for a Git repository for source publishing.

This design is based on Sodia DVI Example Design. And, it is also based on The Golden Hardware Reference Design (GHRD) for Sodia Evaluation Board.

• About the DVI Example description refer to here.
• About the GHRD description refer to here.

Added interfaces and components is following:

• I2S Interfaces for data Input and output for WM8731
  
  • I2S Interface: i2s_wrapper (Qsys compliant user compnent)
    • Playback (TX) FIFO: playback_fifo
    • Capture (RX) FIFO: capture_fifo

Design Information

Note: Contents in this page that highlighted in red and bold font is added for this design.

Block Diagram of HW Design

MPU Address Maps

This section presents the address maps as seen from the MPU (A9) side. Please note that address map is changed from v16.1. This page described NEW address map. For legacy address map [ Click Here].

HPS-to-FPGA Address Map

The memory map of soft IP peripherals, as viewed by the microprocessor unit (MPU), starts at HPS-to-FPGA address offset 0xC000_0000. The following table lists the offset of each peripheral in the FPGA portion of the SoC.

Peripheral	Qsys Address Offset	MPU View	Size (bytes)	Attribute
onchip_memory2_0	0x0	0xc000_0000	64K	On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table.

Peripheral	Qsys Address Offset for mm_bridge	Qsys Address Offset from mm_bridge	MPU View	Size (bytes)	Attribute
i2s.apb_slave_clkctl	0x4_0000	0x0_0000	0xff24_0000	8	I2S Wrapper clkctl
i2s.apb_slave_output	0x4_0000	0x0_0020	0xff24_0020	8	I2S Wrapper output
jtag_uart	0x4_0000	0x2_0000	0xff26_0000	8	JTAG UART console
sysid_qsys	0x4_0000	0x2_0008	0xff26_0008	8	Unique system ID
led_pio	0x4_0000	0x2_0040	0xff26_0040	8	LED output display
dipsw_pio	0x4_0000	0x2_0080	0xff26_0080	8	DIP button input
button_pio	0x4_0000	0x2_00c0	0xff26_00c0	8	Push button input
vfr	0x4_0000	0x2_0100	0xff26_0100	128	Frame Reader (for DVI output)
ILC	0x4_0000	0x3_0000	0xff27_0000	256	Interrupt Latency Counter

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGAfabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral	Qsys Address Offset for mm_bridge	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	-	0x0	64K	On-chip RAM
i2s_apb_slave_clkctl	0x4_0000	0x0000_0000	8	I2S Wrapper clkctl
i2s.apb_slave_output	0x4_0000	0x0000_0020	8	I2S Wrapper output
jtag_uart	0x4_0000	0x0002_0000	8	JTAG UART console
sysid_qsys	0x4_0000	0x0002_0008	8	Unique system ID
led_pio	0x4_0000	0x0002_0040	8	4 LED outputs
dipsw_pio	0x4_0000	0x0002_0080	8	2 DIP switch inputs
button_pio	0x4_0000	0x0002_00c0	8	2 push button inputs
vfr	0x4_0000	0x0002_0100	128	Frame Reader (for DVI output)
ILC	0x4_0000	0x0003_0000	256	Interrupt Latency Counter

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Peripheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0[0]	2 DIP switch inputs
button_pio	f2h_irq0[1]	2 push button inputs
jtag_uart	f2h_irq0[2]	JTAG UART
cvo_ii	f2h_irq0[3]	Clocked Video Output
vfr	f2h_irq0[4]	Frame Reader

The interrupt sources are also connected to an Interrupt Latency Counter module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.

DMA-330 Peripheral Request Signal Routing

The HPS DMAC (ARM DMA-330) can use the peripheral request interface signals for get sync a transport timing. The following table lists the purpose of peripheral request exported to the FPGA side.

Peripheral Request ID	Name	Connect to
0	f2h_dma_req0	I2S Wrapper (Playback I/F)
1	f2h_dma_req1	I2S Wrapper (Capture I/F)
2	f2h_dma_req2	Export to FPGA side, but not connected
3	f2h_dma_req3	Export to FPGA side, but not connected

Reference Designs

Item	Rev.	Download	Note
HW RLINEeference Design	v1.0	sodia_dvi_audio_ghrd_v16.1.0.zip	Quartus Prime Standard Edition v16.1 This design is based on the HW Reference Design v1.1 (sodia_ghrd_v16.1.0.zip)
Linux SD Card Image	v1.0	sodia_xfce_audio_4.1.33-ltsi.tgz	Linux Kernel : v4.1.33-ltsi Rootfs : Angstrom 2015.12

How to Demo

Preparing

To perform this demonstration, you need to prepare the following:

• Mpression Sodia Evaluation Kit (Board, Power Cable(A/C Adaptor), USB-miniB Cable)
• Speaker or Earphone
• SD/SDHC Card (4GB or larger)
• HD Display (DVI Interface / HD(720p) or higher)
• USB-HID (Keyboard and Mouse with USB-Hub)

Download the Linux SD card image on this page. And, please write to the SD card by the following method.

1. Unzip the downloaded file(.tgz) and output the image file(.img).

$ tar -xzvf sodia_xfce_audio_*.tgz

2. Write image file to the SD card

From Linux PC:
$ sudo dd if=sodia_xfce_audio_*.img of=/dev/mmcblk0 bs=1M

From Windows PC:
You can use Win32DiskImager tool

The files required for the demo are all included in the SD card image.
The FPGA configuration data (RBF) is also included in the SD card image.
So, just write the SD card and you're ready to go.

Board Setup

• MSEL (J7)
  You need to set MSEL is FPP mode for FPGA configuring from HPS. Please set MSEL as follows:

• BSEL & CSEL
  For SD Card Boot. You need to set BSEL & CSEL as follows:

• USB UART (UART to USB) (CN11)
  Use as console. Please connect to host PC using usb cable.
  
  
• SD card slot (CN13)
  Please insert prepared SD card before power on.
  
  
• DVI OUT (CN9)
  Use as display output. Please connect to display using DVI cable (720p).
  
  
• USB 2.0 HOST (CN12)
  Use as connect to HID. Please connect to keyboard and mouse via USB-Hub.
  
  
• LINE OUT (CN8)
  Use as sound output. Please connect to speaker or earphone.
  
  
• DCIN Power (CN14) and Power Switch (S7)
  Make sure the power switch S7 on the board is turned OFF.
  Then, Connect 12V power supply cable to DCIN (CN14).

Steps

1. Power ON and wait for the Boot Up.

Turn ON the Power Switch(S7). When the power is on, the boot starts with the log display to the terminal.

U-Boot SPL 2013.01.01 (Aug 09 2017 - 13:08:33)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: Initializing SDRAM ECC
SDRAM: ECC initialized successfully with 1511 ms
SDRAM: ECC Enabled
ALTERA DWMMC: 0

U-Boot 2013.01.01 (Aug 09 2017 - 13:08:53)

CPU   : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C:   ready
DRAM:  1 GiB
MMC:   ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net:   mii0
Warning: failed to set MAC address

Hit any key to stop autoboot:  5  4  3  2  1  0 
reading u-boot.scr
377 bytes read in 4 ms (91.8 KiB/s)
## Executing script at 02000000
reading output_files/soc_system.rbf
2704404 bytes read in 130 ms (19.8 MiB/s)
## Starting application at 0x3FF795A4 …
## Application terminated, rc = 0x0
reading zImage
4344496 bytes read in 202 ms (20.5 MiB/s)
reading soc_system.dtb
25600 bytes read in 5 ms (4.9 MiB/s)
## Flattened Device Tree blob at 00000100
   Booting using the fdt blob at 0x00000100
   Loading Device Tree to 03ff6000, end 03fff3ff … OK

Starting kernel …

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Linux version 4.1.33-ltsi-altera (altsoc@D-ALT12088-01) (gcc version 5.2.1 20151005 (Linaro GCC 5.2-2015.11-2) ) #1 SMP Fri Aug 25 14:01:22 JST 2017
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine model: Altera SOCFPGA Cyclone V
：

2. Boot Complete.

When the boot is complete, the terminal displays the following:

.---O---.                                           
|       |                  .-.           o o        
|   |   |-----.-----.-----.| |   .----..-----.-----.
|       |     | __  |  ---'| '--.|  .-'|     |     |
|   |   |  |  |     |---  ||  --'|  |  |  '  | | | |
'---'---'--'--'--.  |-----''----''--'  '-----'-'-'-'
                -'  |
                '---'

The Angstrom Distribution cyclone5 ttyS0

Angstrom v2015.12 - Kernel 4.1.33-ltsi-altera

cyclone5 login:

You can log in without a password at root. If you are connected to an HD display, the FXCE desktop is displayed in a log on state.

3. Turn off the mute setting for the sound output.

In the default state, the sound output is muted. Please unmute it with the following command.

# amixer -c 0 cset numid=14 on

It can also be configured from the Audio Mixer application in the desktop environment.

Start the Audio Mixer from Multimedia under the Application menu.
Next, check on the check box of "Output Mixer HiFi" from the "Select Controls" shown in RED.
In this state, it can switch the MUTE ON/OFF via check box of "Output Mixer HiFi" on "Swtiches" TAB shown in BLUE.

4. Playback sound files (Execute mplayer)

The audio-only file (.mp3) and the video file (.avi) are stored in the following location:

• /home/root/sounds_and_movies/

Each file can be used for testing, but be careful with license of contents. The licenses applied to each file are listed in the README.txt.

Sound TEST

# mplayer /home/root/sounds_and_movies/ABrighterHeart.mp3

Sound and Movie TEST

# mplayer /home/root/sounds_and_movies/big_buck_bunny_480p_stereo.avi

You can also run from the UART terminal if you only have audio. If you want to see the video, run it from the desktop terminal.