Overview

This page presents an example of enabling HPS to configure FPGA in u-boot and Linux operating system user stage on a S10 SoC Development Board. It covers:

• Modify S10 GHRD to enable HPS boot first in Quartus Prime Pro software tool
  • Merging hardware .sof file and First Stage Bootloader (FSBL)
  • Generate peripherals Raw Binary File (RBF) for initial configuration and core RBF for HPS to configure FPGA in u-boot and Linux
• u-boot
  • Configure FPGA with core RBF
• Linux
  • Modify Linux kernel code to enable overlay
  • Configure FPGA with core RBF using overlay

Take note that:

• Both peripherals RBF and core RBF MUST be generated from the same Intel Quartus Prime version, this includes patches installed if applicable
• This design example used JTAG to configure S10 FPGA with the initial RBF bitstream and Core RBF is stored in SD card
• To boot initial bitstream from QSPI, please refer to Stratix 10 SoC Single QSPI Flash Boot

Release Contents

The following prebuild files are based on Stratix 10 Development Board ES edition - 1SX280LU2F50E2VGS2. It is available as part of this design example:

Folder	File	Description
bin	s10_sdimage.tar.gz	Binaries archive for this design example. It contains all the require components for quick start purpose: sdimage.img - SD card image file that comes with u-boot, Rootfs, Kernel image and Device Tree Blob ghrd_1sx280lu2f50e2vg_hps.hps.rbf - initial bit stream for HPS boot first mode ghrd_1sx280lu2f50e2vg_hps.core.rbf - core RBF file for HPS to configure FPGA in u-boot/Linux
hw	s10_soc_devkit_ghrd_hps_boot_first.tar.gz	Hardware design example zip file, consist of necessary system file to generate sof image
src	overlay.patch	Linux patch to enable overlay
^	configure_fpga.sh reconfigure_fpga.sh	Script to program FPGA in Linux, prebuild in sdimage.bin

Quick start guide

The following section describes the step to leverage prebuild files to exercise the feature.

1. Setup up S10 Development Board in JTAG configuration mode
   • SW1: 1:OFF, rest:ON
   • SW2: 1:ON 2:ON 3: ON 4: OFF
   • SW3: all OFF
   • SW4: 1:ON 2:OFF 3:OFF 4:ON
2. Prepare SD card by following the Booting Linux with SD Card Image. Untar s10_sdimage.tar.gz, program sdimage.bin into SD card then copy ghrd_1sx280lu2f50e2vg_hps.core.rbf into SD card.
3. Slot in the SD card. Power up the board and program ghrd_1sx280lu2f50e2vg_hps.hps.rbf file with Quartus Prime Programmer Pro.
4. Configure the FPGA in U-boot:
   • Note that you must use the address range between 0x100000 (1MB offset) to 0x20000000 (512MB offset) for core RBF bitstream DDR address.
   • Stop autoboot by hitting any key and goto u-boot stage.
   • Use the following command to program FPGA in u-boot:
     • Load the core RBF bit stream from MMC to DDR memory at 0x100000
       • fatload mmc 0:1 100000 ghrd_1sx280lu2f50e2vg_hps.core.rbf
     • Program the bit stream loaded at DDR memory address 0x100000 into FPGA
       • fpga load 0 100000 ${filesize}

         SOCFPGA_STRATIX10 # fatload mmc 0:1 100000 ghrd_1sx280lu2f50e2vg_hps.core.rbf 
         reading ghrd_1sx280lu2f50e2vg_hps.core.rbf 
         3174400 bytes read in 223 ms (13.6 MiB/s) 
         SOCFPGA_STRATIX10 # fpga load 0 100000 ${filesize} 
         .... 
         FPGA reconfiguration OK! 

5. Configure the FPGA in Linux:
   • Allow the U-boot to load Linux and login using 'root'
   • Modify the prebuild script to executable and use it to configure FPGA in Linux:
     • configure_fpga.sh
       • $ mkdir /sys/kernel/config/device-tree/overlays/0
       • $ echo socfpga_stratix10_ovl1.dtb > /sys/kernel/config/device-tree/overlays/0/path

         root@stratix10swvp:~# chmod 744 configure_fpga.sh 
         root@stratix10swvp:~# ./configure_fpga.sh 
         [ 214.835187] fpga_manager fpga0: writing soc_s10_ovl1.rbf to Stratix10 SOC FPGA Manager 
         [ 214.985699] Stratix10 SoC FPGA manager soc:fpga-mgr@0: Requesting full reconfiguration.

   • If you would like to re-configure the FPGA, use the below prebuild script to remove and rebuild overlay:
     • reconfigure_fpga.sh
       • $ rmdir /sys/kernel/config/device-tree/overlays/0
       • $ mkdir /sys/kernel/config/device-tree/overlays/0
       • $ echo socfpga_stratix10_ovl1.dtb > /sys/kernel/config/device-tree/overlays/0/path

         root@stratix10swvp:~# chmod 744 reconfigure_fpga.sh 
         root@stratix10swvp:~# ./reconfigure_fpga.sh 
         [ 907.894386] fpga_manager fpga0: writing soc_s10_ovl1.rbf to Stratix10 SOC FPGA Manager 
         [ 907.911722] Stratix10 SoC FPGA manager soc:fpga-mgr@0: Requesting full reconfiguration.

Prerequisites

Hardware requirement

• S10 SoC Development Board

Software requirement

• Quartus Prime Pro 18.1
• S10 GHRD 18.1
• Linux host PC with Ubuntu 16.04 LTS (or any newer version)

Getting Started

The following section provides the step-by-step instructions to guide user from create the design to generate programming files and exercise the feature.

• Setup HPS boot first in Quartus Prime Pro
• Generate FSBL
• Integrating u-boot FSBL to .sof file
• Generate RBF for FPGA initial configuration
• Configuring the FPGA using u-boot SSBL
• Modify Linux kernel drivers
• Configure the FPGA via S10 FPGA manager and device tree overlay

Setup HPS boot first in Quartus Prime Pro

1. Download S10 GHRD design example from s10_soc_devkit_ghrd.tar.gz or copy from SoCEDS directory ../18.1/embedded/examples/s10_soc_devkit_ghrd
2. Open project with Quartus Prime Pro 18.1. Select device according to the S10 SoC Development board revision.
   • Refer to this link for S10 SoC Development Board revision
3. Specify the boot mode through the HPS/FPGA configuration order pulldown in the Configuration project category.
   • HPS First: This option selects HPS Boot First. The SDM only configures the I/O required for the HPS SDRAM, and then loads the FSBL into the HPS onchip RAM before releasing the HPS from reset. The FPGA core and the other unused I/O, remain unconfigured
   • Disable use configuration device option
4. Recompile project to generate hardware .sof file

Generate First Stage Bootloader (FSBL)

1. Please refer to S10 GSRD User Manual: Compiling the U-boot FSBL and SSBL
2. In this design example, we will leverage the default u-boot source from S10 GHRD directory: s10_soc_devkit_ghrd\software\u-boot

Integrating u-boot FSBL to .sof file

1. For detail steps, please refer to S10 GSRD User Manual: Compiling the Hardware Design and Integrating U-boot FSBL
2. During full compilation, the Intel Quartus Prime Pro Edition generates the data in the HPS FSBL handoff binary based on the settings inside the Platform Designer. The file contains information on:
   • HPS pin multiplexing configuration, including HPS dedicated I/O settings and export to FPGA settings
   • HPS clock configuration
   • HPS SSBL boot source
3. Run below command to merge both .sof and FSBL:
   • $ quartus_cpf --bootloader=<hex_file> <input_sof> <output_sof>

     $ quartus_cpf --bootloader=software/u-boot/spl/u-boot-spl-dtb.ihex output_files/ghrd_1sx280lu2f50e2vg.sof output_files/ghrd_1sx280lu2f50e2vg_hps.sof

Generate RBF for FPGA initial configuration

1. In the HPS boot first mode, FPGA is required to be configure by a .rbf file that contain an initial bitstream to set the HPS EMIF I/O and HPS FSBL.
2. To generate the RBF file, type the Intel Quartus Prime Pro Edition Convert Programmer tool command as shown below:
   • quartus_cpf -c --hps -o bitstream_compression=on <input_sof> <output_rbf>

     $ quartus_cpf -c --hps -o bitstream_compression=on ghrd_1sx280lu2f50e2vg_hps.sof ghrd_1sx280lu2f50e2vg_hps.rbf

   • Below RBF files are generated:
     • ghrd_1sx280lu2f50e2vg_hps.hps.rbf – bitstream for initial configuration through JTAG programming
     • ghrd_1sx280lu2f50e2vg_hps.core.rbf – to be configured by HPS in u-boot or Linux
3. Program ghrd_1sx280lu2f50e2vg_hps.hps.rbf to the board with Quartus Prime Pro programmer

Configuring the FPGA using u-boot SSBL

1. Copy the ghrd_1sx280lu2f50e2vg_hps.hps.rbf into SD card FAT32 partition.
2. After program the initial peripheral .rbf file, stop autoboot by hitting any key and go to u-boot console.
3. Load the RBF image from SD card by using the 'fpga load <devnum> <loadaddr> <filesize>' command to program the bit stream into the FPGA from the DDR memory. Here is an example of how to program the FPGA with the bit stream stored in MMC by using u-boot command prompt :
   • Note that you must use the address range between 0x100000 (1MB offset) to 0x20000000 (512MB offset) for core RBF bitstream DDR address.
   • Load the core RBF bit stream from MMC to DDR memory at 0x100000
     • fatload mmc 0:1 100000 <example.rbf>
   • Program the bit stream loaded at DDR memory address 0x100000 into FPGA
     • fpga load 0 100000 ${filesize}

       SOCFPGA_STRATIX10 # fatload mmc 0:1 100000 ghrd_1sx280lu2f50e2vg_hps.core.rbf 
       reading ghrd_1sx280lu2f50e2vg_hps.core.rbf 
       3174400 bytes read in 223 ms (13.6 MiB/s) 
       SOCFPGA_STRATIX10 # fpga load 0 100000 ${filesize} 
       .... 
       FPGA reconfiguration OK!

Modify Linux kernel drivers

1. Please refer to S10 GSRD User Manual: Compiling Linux for Stratix 10 on tool chain setup and cloning git trees to build Linux kernel.
2. Checkout socfpga-4.9.78-ltsi branch after git clone. Please refer to GSRD 18.1 release notes for tagging information.

   $ git checkout ACDS18.1_REL_GSRD_PR

3. If you would like to use the patch to create overlay, you may copy the patch into linux-socfpga directory. Apply patch with below command:

   $ patch -p1 -i overlay.patch

4. If you would like to modify the kernel drivers manually, you may follow steps 5 and 6.
5. In the file /arch/arm64/boot/dts/altera/Makefile, add a second .dtb file with the following command:
   

   dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb socfpga_stratix10_ovl1.dtb

6. Create a new .dts file named socfpga_stratix10_ovl1.dts and add the overlay information of the RBF file into the file as shown below:

   /dts-v1/; 
   /plugin/; 
   / {

   fragment@0 {

   target-path = "/soc/base_fpga_region";
   #address-cells = <1>;
   #size-cells = <1>;
   __overlay__ {

   #address-cells = <1>;
   #size-cells = <1>;
   firmware-name = "soc_s10_ovl1.rbf";
   config-complete-timeout-us = <30000000>;
   };

   }; }; 

7. After that, rebuild kernel image and DTB with the following command:

   $ make s10_devkit_defconfig 
   $ make

8. The following files are generated:

   File name	Location	Description
   Image	arch/arm64/boot/	Linux image file
   socfpga_stratix10_socdk.dtb	arch/arm64/boot/dts/altera/	DTB for kernel boot up
   socfpga_stratix10_ovl1.dtb	arch/arm64/boot/dts/altera/	DTB too triggering FPGA manager to configure FPGA

   1. Copy and replace existing Image and socfpga_stratix10_socdk.dtb in the SD card.
   2. Rename ghrd_1sx280lu2f50e2vg_hps.core.rbf to soc_s10_ovl1.rbf and copy into SD card /lib/firmware directory in Ext4 partition including the socfpga_stratix10_ovl1.dtb.
   3. Boot up S10 SoC development board and log in to user stage as root user.

   Configure the FPGA via S10 FPGA manager and device tree overlay

   1. Use below command to apply the overlay and program the soc_s10_ovl1.rbf file

      root@stratix10swvp:~# mkdir /sys/kernel/config/device-tree/overlays/0 
      root@stratix10swvp:~# echo socfpga_stratix10_ovl1.dtb > /sys/kernel/config/device-tree/overlays/0/path 
      [ 214.835187] fpga_manager fpga0: writing soc_s10_ovl1.rbf to Stratix10 SOC FPGA Manager 
      [ 214.985699] Stratix10 SoC FPGA manager soc:fpga-mgr@0: Requesting full reconfiguration. 

   2. If you want to apply the overlay again, first you need to remove it and re-apply again

      root@stratix10swvp:~# rmdir /sys/kernel/config/device-tree/overlays/0 
      root@stratix10swvp:~# mkdir /sys/kernel/config/device-tree/overlays/0 
      root@stratix10swvp:~# echo socfpga_stratix10_ovl1.dtb > /sys/kernel/config/device-tree/overlays/0/path 
      [ 907.894386] fpga_manager fpga0: writing soc_s10_ovl1.rbf to Stratix10 SOC FPGA Manager 
      [ 907.911722] Stratix10 SoC FPGA manager soc:fpga-mgr@0: Requesting full reconfiguration. 

   Reference

   • Stratix 10 SoC FPGA BootUser Guide