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Table of Contents
Warping Engine IP - TW200 on Cyclone V ST SoC
Warping Engine IP - TW200 on Cyclone V ST SoC
| Board: | MacnicaSodiaEvaluationBoard |
|---|---|
| State: | running |
| Homepage: | http://www.takumi-corp.com/en |
Video
This movie demonstrates low-latency (short delay) image warping processed by the Image Warping IP TW200 on FPGA.
In the first part, the left frame demonstrates the effect from a low latency (short delay) processing (8ms: approx. 1/2 frame), while the right frame shows a 200ms latency image for comparison.The delay can be set to a desired rate such as a 1/6 or a 1/4 frame (depending on transformation).In the second part, a few other image warping examples processed by TW200.
Introduction - Warping Engine IP TW200
TAKUMI's Warping Engine IPs, including TW200, allow highly flexible image transforms and distortion corrections. TW200 is a performance upgrade to TW100. TW200 is capable of processing transforms and distortion corrections at 120 fps in full HD resolution. A variety of filters (options) including bi-cubic and chromatic aberration are supported with TW200. Its I/O interface is flexibly compatible with AXI Stream / Bus, and image interfaces including Displayport and HDMI. TW200 is best suited to such applications as in-car systems (for camera lens distortion corrections or HUD), projectors, surveillance camera, and VR Hed set.Overview - Warping Engine IP TW200
| Resolution | XGA - FHD, WUXGA |
| Image Format | RGB / YUV |
| Key Features | Image warping (any shape), up/down scaling, rotating |
| Performance (frame rate) | 30 - 120 fps |
| Logic size | 32KLE (minimum) |
Block Diagram
Development Environment
| Hardware | Macnica Sodia Board + Macnica 100Base-T1 HSMC Card |
| FPGA Tools | Intel Quartus Prime Version 16.1.0 |
| OS | Linux for Macnica Sodia Board |
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