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What is an SVD file?
How to generate the SVD file?
Validate the SVD file
Integrating an SVD file into your system
An example design

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Using CMSIS with Custom FPGA Logic
Describe format of CMSIS-SVD file, integrate the SVD file into the system, and expose the register of custom logic in the register view of DS-5.

25 March 2019 - 06:16 | Version 16 | QiHuang | Example Design | CMSIS, FPGA, HPS, SVD

State:	closed
Members:	QiHuang, SueCozart

This project intends to describe what a CMSIS-SVD file is, how to integrate CMSIS-SVD with custom FPGA logic into the SoC system, and how to expose the custom logic registers in the register view of DS-5 debug perspective.

What is an SVD file?

A full description of the SVD file function and structure can be found at https://www.keil.com/pack/doc/CMSIS/SVD/html/svd__outline_pg.html.

How to generate the SVD file?

If you know the architecture of the svd file, then you can write it manually. To help you write the correct xml format svd, you can use schema from http://www.w3.org/2001/XMLSchema-instance.
Some of EDA vendors provide the tools to easily extract the svd file from your RTL design. One of the example is Magillem: http://www.magillem.com/wp-content/uploads/2015/02/Magillem-Register-View_2.2.pdf

Validate the SVD file

Keil provides a tool called SVDConv, which is a command-line utility to validate CMSIS-SVD files and to generate CMSIS-compliant device header files. SVDConv.exe is distributed with the ARM::CMSIS Pack (in the CMSIS\Utilities directory) together with the CMSIS-SVD schema file. This utility can help validate the manually-generated SVD file, but is not necessary.

SVDConv.exe performs the following operations:

Checks the syntactical and structural compliance with the specified CMSIS-SVD format.
Checks the consistency, correctness, and completeness of the CMSIS-SVD file against the CMSIS-SVD schema file.
Generates CMSIS-compliant device header files, which can be used for software development.

Reference:

Integrating an SVD file into your system

Qsys allows IP component designers to specify register map information on their slave interfaces. These components and their internal register descriptions can be added into the generated .svdfile.

To specify an internal register map, the IP component designer must write and generate their own .svd file and attach it to the slave interface using the following command:

set_interface_property<slave interface> CMSIS_SVD_FILE<file path>

The CMSIS_SVD_VARIABLES interface property allows for variable substitution inside the .svd file. You can dynamically modify the character data of the .svdfile by using the CMSIS_SVD_VARIABLES property.

For example:

For an HPS slave component in altera_avalon_sysid_qsys_hw.tcl, the property calls the altera_avalon_sysid_qsys.svd file, and configures its control slave interface with the registers defined in the svd file:

set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera sopc_builder_ip altera_avalon_sysid_qsys altera_avalon_sysid_qsys.svd]

set_interface_property control_slave CMSIS_SVD_FILE $svd_path
For an HPS master componentin altera_hps_hw.tcl, the property uses the following instructions to specify the hps svd file:

set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd]

set address_group hps

Use the instructions to describe the registers for the bridges:

if { $h2f_present } {

……

set_interface_property h2f_axi_master SVD_ADDRESS_GROUP "hps"

set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000

if {!$declared_svd_file} {

set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path

set declared_svd_file 1

}

}

if { $h2f_lw_present } {

…...

if {!$declared_svd_file} {

set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path

set declared_svd_file 1

} }
QSYS calls the master and slaves hw.tcl files and integrates them into a single SVD file.

An example design

Here is an example design to demonstrate how to develop a custom logic component, write the register SVD file, integrate it into the system, and eventually expose the custom logic’s registers in the DS-5 debug perspective.

You can find the example in this attachment:

soc_system_svd.qar

Build a new component from QSYS:
- Specify the component name as “one_reg”.
- Use Menu -- >Templates -- > Add Avalon-MM Simple Slave to generate a simple component with registers (Figure 1)
  
  Figure 1 edit new component
- Click TAB -- > Signals & Interfaces to check the component’s interface signals (Figure 2)
  
  Figure 2 edit signals and interfaces
- Click TAB -- > Files -- > Create Systhesis File from Signals
- Click Finish; this will generate one_reg_hw.tcl
Write the SVD file for the one_reg component. In this example, the svd file describes two registers actually. Place the one_reg.svd in the same directory as the one_reg_hw.tcl.
Add the two instructions into one_reg_hw.tcl

set svd_path [file join [pwd] one_reg.svd]

set_interface_property control_slave CMSIS_SVD_FILE $svd_path
In QSYS, click File -- > Refresh System; this action ensures that QSYS knows that one_reg_hw.tcl has been updated.
In IP Catalog, find your custom logic component “one_reg,” edit and place it in your system. Generate HDL in QSYS to integrate one_reg.svd into the soc_system_hps_0_hps.svd
Open DS-5,and in the debug configuration tab, for the field of "add peripheral description from directory," point to the hps synthesis directory of soc_system_hps_0_hps.svd (see Figure 3).

Figure 3 add peripheral description files from HPS synthesis directory
In the DS-5 debug perspective, you can then see the Avalon slave one_reg register (see Figure 4).

Figure 4 Register view in DS-5

With the method addressed in this example, one can integrate a custom logic into the HPS system and expose its registers in the DS-5 debug perspective.