This demonstration shows a digital camera reference design using the 5-Megapixel CMOS sensor module and 7-inch LCD modules on the MTL2 with the Atlas-Soc Kit.. The FPGA logic accesses the HPS DDR3 memory in this system as a buffer.

The system block of the demonstration is shown as below.

The CMOS sensor module sends the raw image data to the FPGA, and the FPGA on the board handles image processing part and converts the data to RGB format. As there is no external memory on FPGA side on DE0_Nano_SoC Board, the demonstration uses the DDR3 Memory on the HPS as a frame buffer to store the video data. The FPGA access the DDR3 on HPS through the F2H _SDRAM axi Bridge. The HPS SDRAM Controller in the HPS should be initialized by the preloader code before the FPGA code running. The frame buffer IP read the video data and display it on the LCD.

Linix Image file : DE0_SoC_MTL2_D5M.zip

Quartus Project : DE0_NANO_VIP_Camera.zip

Set up the demonstration

1. Download the image file and extract it
2. Connect your microSD card to the PC and write the image file to the SD card with the Win32DiskImager.exe tool
3. Connect D5M module to the GPIO1 port (JP7) and connect the MTL2 module to the GPIO0 port (JP1) on the DE0_Nano_SoC board as below

4. Set the MSEL[4..0] to 00000 on DE0_Nano_SoC Board as below

5. Insert the microSD card to the SD card Socket
6. Power on the board, please wait for the HPS initial the DDR3 controller and configure the FPGA, then you will find the video display on the LCD