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Multiprocessor Nios V/m system: creating your first GeMRTOS application
Quick Start Guide on how to create a multiprocessor system with Nios V processor and GeMRTOS support -
Intel® Agilex® 7 I-Series Transceiver-SoC Development Kit (4x F-Tile) System Example Design With IEEE1588 PTP (25GE/10GE 2-Port)
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Setting up and Using Bridges on Agilex 7 SoC
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Agilex 7 SoC With eMMC Storage On HPS
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Stratix 10 SoC with eMMC Storage on HPS
| Board: | Arria10SoCDevelopmentKit |
|---|---|
| Tools Version: | 17.0 |
| State: | running |
| Members: | RK29 |
- Image Storage: Capturing the UVC camera input video stream as JPEG image in the µSD. OpenCV support is provided for the image processing (Grayscale & Canny).
- Video Streaming to DP output: UVC camera input frames are streamed to the DP display (1280 X 720) via FPGA AXI bridges.
- Video Streaming over Ethernet: UVC camera input frames (1280 X 720) are streamed over Ethernet.
- The below are the interfaces used by HPS to communicate with the FPGA Fabric to control and transfer the data for below applications:
- HPS Cortex A9 ARM core to capture the camera input @ 720P resolution
- HPS DDR4 controller to store and write the data to FPGA Frame buffer
- Frame buffer II IP configured in Frame reader only mode
- Nios Soft processor to configure and initialize the DP source IP core
- Altera Transceiver core configured at 5.4 Gbps to transmit the Four Lane Display port data
- On Chip memory to store the Nios software elf
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