Board: Altera Arria 10 SoC Board
Tools Version: 17.0
State: running
Members: RaviKishore29

.Purpose

The purpose of this project is to demonstrate the video and image processing Implementation in HPS on Intel Arria 10 SoC Development Kit.

Overview

This design is an example that shows how to use both HPS and FPGA portion of the SoC concurrently to implement a complex function and utilizing dual-core ARM Cortex-A9 core for Video and Image processing. Below features are supported:
  • Image Storage: Capturing the UVC camera input video stream as JPEG image in the µSD. OpenCV support is provided for the image processing (Grayscale & Canny).
  • Video Streaming to DP output: UVC camera input frames are streamed to the DP display (1280 X 720) via FPGA AXI bridges.
  • Video Streaming over Ethernet: UVC camera input frames (1280 X 720) are streamed over Ethernet.
  • The below are the interfaces used by HPS to communicate with the FPGA Fabric to control and transfer the data for below applications:
  • HPS Cortex A9 ARM core to capture the camera input @ 720P resolution
  • HPS DDR4 controller to store and write the data to FPGA Frame buffer
  • Frame buffer II IP configured in Frame reader only mode
  • Nios Soft processor to configure and initialize the DP source IP core
  • Altera Transceiver core configured at 5.4 Gbps to transmit the Four Lane Display port data
  • On Chip memory to store the Nios software elf

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