Warping Engine IP Demo on Macnica Helio
Warping Engine IP - TW100 Demo on Cyclone V SoC FPGA

13 Jun 2017 - 10:54 | Version 18 | | |

Video

This movie demonstrates that the fish-eye camera image is corrected (warped) in real time through the Warping Engine IP integrated in the FPGA and output to the display device via DVI terminal.

Introduction - Warping Engine IP TW100

Warping Engine IP enables image transform and distortion correction with high flexibility. The IP allows image distortion correcting with any erratic shape or high-degree polynomial, which can be fully utilized in a variety of systems including surveillance camera and on-board camera for vehicles that require image correction from the fish-eye camera to the normal image perspectives or even panoramic conversion. The IP can also be used for output image correction for headup displays and projectors.

Overview - Warping Engine IP TW100

Resolution Up to 2048 x 2048
Image Format Input : RGB / YUV  Output: RGB
Key Features Image warping (any shape), up/down scaling, rotating
Performance (frame rate) Over 30fps
Logic size 24KLE (minimum)

Block Diagram

Demo system block diagram

Development Environment

Hardware Macnica Helio Board + Terasic DVI-HSMC board
FPGA Tools Altera Quartus II Version 15.0.1
OS Linux for Macnica Helio Board

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