I8D(DAltera SOCFPGA Cyclone V#!altr,socfpga-cyclone5altr,socfpgachosen5,console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwaitaliases5/soc/ethernet@ff702000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpuscpu@0!arm,cortex-a9ucpucpu@1!arm,cortex-a9ucpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bususocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecell   h  * 1apb_pclk=&&clkmgr@ffd04000 !altr,clk-mgr@clocksosc1H !fixed-clockU}x@osc2H !fixed-clockf2s_periph_ref_clkH !fixed-clockf2s_sdram_ref_clkH !fixed-clock  main_pllH!altr,socfpga-pll-clock*@mpuclkH!altr,socfpga-perip-clk* e H  mainclkH!altr,socfpga-perip-clk* e L  dbg_base_clkH!altr,socfpga-perip-clk* e Pmain_qspi_clkH!altr,socfpga-perip-clk*Tmain_nand_sdmmc_clkH!altr,socfpga-perip-clk*Xcfg_h2f_usr0_clkH!altr,socfpga-perip-clk*\periph_pllH!altr,socfpga-pll-clock *emac0_clkH!altr,socfpga-perip-clk*emac1_clkH!altr,socfpga-perip-clk*per_qsi_clkH!altr,socfpga-perip-clk*per_nand_mmc_clkH!altr,socfpga-perip-clk*per_base_clkH!altr,socfpga-perip-clk*h2f_usr1_clkH!altr,socfpga-perip-clk*sdram_pllH!altr,socfpga-pll-clock *   ddr_dqs_clkH!altr,socfpga-perip-clk* ddr_2x_dqs_clkH!altr,socfpga-perip-clk* ddr_dq_clkH!altr,socfpga-perip-clk* h2f_usr2_clkH!altr,socfpga-perip-clk* mpu_periph_clkH!altr,socfpga-perip-clk* m''mpu_l2_ram_clkH!altr,socfpga-gate-clk* ml4_main_clkH!altr,socfpga-gate-clk* {`l3_main_clkH!altr,socfpga-gate-clk* l3_mp_clkH!altr,socfpga-gate-clk*  ed{`  l3_sp_clkH!altr,socfpga-gate-clk*  edl4_mp_clkH!altr,socfpga-gate-clk*  ed{`  l4_sp_clkH!altr,socfpga-gate-clk*  ed{`dbg_at_clkH!altr,socfpga-gate-clk* eh{`dbg_clkH!altr,socfpga-gate-clk* eh{`dbg_trace_clkH!altr,socfpga-gate-clk* el{`dbg_timer_clkH!altr,socfpga-gate-clk*{`cfg_clkH!altr,socfpga-gate-clk*{`h2f_user0_clkH!altr,socfpga-gate-clk*{` emac_0_clkH!altr,socfpga-gate-clk*{emac_1_clkH!altr,socfpga-gate-clk*{usb_mp_clkH!altr,socfpga-gate-clk*{ e((spi_m_clkH!altr,socfpga-gate-clk*{ ecan0_clkH!altr,socfpga-gate-clk*{ ecan1_clkH!altr,socfpga-gate-clk*{ e gpio_db_clkH!altr,socfpga-gate-clk*{ eh2f_user1_clkH!altr,socfpga-gate-clk*{sdmmc_clkH!altr,socfpga-gate-clk *{!!nand_x_clkH!altr,socfpga-gate-clk *{ nand_clkH!altr,socfpga-gate-clk *{ m##qspi_clkH!altr,socfpga-gate-clk *{ $$ddr_dqs_clk_gateH!altr,socfpga-gate-clk*{ddr_2x_dqs_clk_gateH!altr,socfpga-gate-clk*{ddr_dq_clk_gateH!altr,socfpga-gate-clk*{h2f_user2_clkH!altr,socfpga-gate-clk*{d_can@ffc00000 !bosch,d_can *okayd_can@ffc01000 !bosch,d_can * disabledethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacp   smacirq* 1stmmaceth disabledethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacp   xmacirq* 1stmmacethokayrgmii (!-fpgamgr@0xff706000 !altr,fpga-mgr-1.0altr,fpga-mgr:mmiop`  fpgabridge@0!altr,socfpga-hps2fpga-bridge Dhps2fpga*fpgabridge@1!altr,socfpga-lwhps2fpga-bridge Dlwhps2fpga*fpgabridge@2!altr,socfpga-fpga2hps-bridge Dfpga2hps*i2c@ffc04000!snps,designware-i2c@  *okayJUmi2c@ffc05000!snps,designware-i2cP  *okayJUmeeprom@50!microchip,24aa025e64Prtc@68 !nxp,pcf8523hi2c@ffc06000!snps,designware-i2c`  * disabledi2c@ffc07000!snps,designware-i2cp  * disabledgpio@ff708000!snps,dw-apb-gpiop*okaygpio-controller@0!snps,dw-apb-gpio-port  gpio@ff709000!snps,dw-apb-gpiop*okaygpio-controller@0!snps,dw-apb-gpio-port  ""gpio@ff70a000!snps,dw-apb-gpiop*okaygpio-controller@0!snps,dw-apb-gpio-port  l2-cache@fffef000!arm,pl310-cachesyscon  &  dwmmc0@ff704000!altr,socfpga-dw-mshcp@  * !1biuciu%:slot@0 R"[nand@ff900000!denali,denali-nand-dtenand_datadenali_reg  o*#x disabledpartition@nand-bootDNAND Flash Boot Area 8MBpartition@nand-rootfs'DNAND Flash jffs2 Root Filesystem 128MBpartition@nand-128DNAND Flash 128 MBpartition@nand-64DNAND Flash 64 MBpartition@nand-32DNAND Flash 32 MBpartition@nand-16DNAND Flash 16 MBsram@ffff0000 !mmio-sram%%pmu!arm,cortex-a9-pmu cti0@ff118000!arm,coresight-cticti1@ff119000!arm,coresight-ctispi@ff705000 !cadence,qspipP  *$okayn25q256@0!n25q25622 partition@qspi-bootDFlash 0 Raw Datapartition@qspi-rootfsDFlash 0 jffs2 Filesystemrstmgr@ffd05000!altr,rst-mgrsysconPsdrctl@0xffc25000!altr,sdr-ctlsysconPsdramedac@0!altr,sdram-edac  'l2edac@xffd08140 !altr,l2-edacЁ@ $%ocramedac@ffd08144!altr,ocram-edacЁD% l3regs@0xff800000!altr,l3regssysconspi@fff00000!snps,dw-spi-mmio  &&&*spidev@0!spidev5spi@fff01000!snps,dw-spi-mmio  &&&* disabledspidev@0!spidev5sysmgr@ffd08000!altr,sys-mgrsysconЀ@@Ѐtimer@fffec600!arm,cortex-a9-twd-timer   *'timer0@ffc08000!snps,dw-apb-timer-sp  *1timertimer1@ffc09000!snps,dw-apb-timer-sp  *1timertimer2@ffd00000!snps,dw-apb-timer-osc  *1timertimer3@ffd01000!snps,dw-apb-timer-osc  *1timerserial0@ffc02000!snps,dw-apb-uart   PZ*okayserial1@ffc03000!snps,dw-apb-uart0  PZ* disabledusbphy@0g!usb-nop-xceivokay))usb@ffb00000 !snps,dwc2  }*(1otgr) wusb2-phy    disabledusb@ffb40000 !snps,dwc2  *(1otgr) wusb2-phy   okaywd@ffd02000 !snps,dw-wdt   *okaywd@ffd03000 !snps,dw-wdt0  * disabled #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentranges#dma-cells#dma-channels#dma-requestsinterruptsnr-irqsnr-valid-periclocksclock-namescopy-align#clock-cellsclock-frequencydiv-regfixed-dividerclk-gatestatusinterrupt-namesmac-addressphy-modephy-addrsnps,phy-addrrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-pssnps,max-mtutransportlabelspeed-modei2c-sda-falling-time-nsi2c-scl-falling-time-nspagesizegpio-controller#gpio-cellssnps,nr-gpioscache-unifiedcache-levelarm,tag-latencyarm,data-latencyfifo-depthnum-slotssupports-highspeedbroken-cdaltr,dw-mshc-ciu-divaltr,dw-mshc-sdr-timingcd-gpiosbus-widthreg-namesdma-maskhave-hw-ecc-fixupext-decodernum-chipselectbus-numspi-max-frequencym25p,fast-readpage-sizeblock-sizeread-delaytshsl-nstsd2d-nstchsh-nstslch-nsiramtx-dma-channelrx-dma-channelenable-dmacpu1-start-addrreg-shiftreg-io-width#phy-cellsphysphy-namesenable-dynamic-fifohost-rx-fifo-sizehost-perio-tx-fifo-sizehost-nperio-tx-fifo-sizedma-desc-enable